Datasheet

TLV320ADC3001
SLAS548C –OCTOBER 2008– REVISED APRIL 2011 www.ti.com
Page 0 / Register 28: Data Slot Offset Programmability 1 (Ch_Offset_1)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 0000 0000: Offset = 0 BCLKs. Offset is measured with respect to WCLK rising edge in DSP mode.
(1)
0000 0001: Offset = 1 BCLKs
0000 0010: Offset = 2 BCLKs
...
1111 1110: Offset = 254 BCLKs
1111 1111: Offset = 255 BCLKs
(1) Usage controlled by page 0 / register 38, bit D0
Page 0 / Register 29: ADC Interface Control 2
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R/W 0000 Reserved. Do not write any value other than reset value.
D3 R/W 0 0: BCLK is not inverted (valid for both primary and secondary BCLK).
1: BCLK is inverted (valid for both primary and secondary BCLK).
D2 R/W 0 0: BCLK and WCLK active even with codec powered down: disabled (valid for both primary and
secondary BCLK)
1: BCLK and WCLK active even with codec powered down: enabled (valid for both primary and
secondary BCLK)
D1–D0 R/W 10 00: Reserved. Do not use.
01: Reserved. Do not use.
10: BDIV_CLKIN = ADC_CLK (generated on-chip)
11: BDIV_CLKIN = ADC_MOD_CLK (generated on-chip)
Page 0 / Register 30: BCLK N Divider
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: BCLK N divider is powered down.
1: BCLK N divider is powered up.
D6–D0 R/W 000 0001 000 0000: CLKOUT divider N = 128
000 0001: CLKOUT divider N = 1
000 0010: CLKOUT divider N = 2
...
111 1110: CLKOUT divider N = 126
111 1111: CLKOUT divider N = 127
Page 0 / Register 31 Through Page 0 / Register 33: Reserved
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R XXXX XXXX Reserved. Do not write to this register.
Page 0 / Register 34: I
2
S Sync
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: Internal logic is enabled to detect the I
2
C hang and react accordingly.
1: Internal logic is disabled to detect the I
2
C hang.
D6 R 0 0: I
2
C hang is not detected.
1: I
2
C hang is detected. D6 bit is cleared to "0" only by reading this register
D5 R/W 0 0: I
2
C general-call address is ignored.
1: Device accepts I
2
C general-call address.
D4–D2 R 000 Reserved. Do not write any value other than reset value.
D1 R/W 0 0: Re-sync logic is disabled for ADC.
1: Re-sync stereo ADC with codec interface if the group delay changed by more than ±ADC_f
S
/4.
D0 R/W 0 0: Re-sync is done without soft-muting the channel for ADC.
1: Re-sync is done by internally soft-muting the channel for ADC.
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