Datasheet

TLV320ADC3001
www.ti.com SLAS548C –OCTOBER 2008– REVISED APRIL 2011
Page 0 / Register 4: Clock-Gen Multiplexing
(1)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D4 R 0000 Reserved. Do not write any value other than reset value.
D3–D2 R/W 00 00: PLL_CLKIN = MCLK (device pin)
01: PLL_CLKIN = BCLK (device pin)
10: Reserved. Do not use.
11: PLL_CLKIN = logic level 0
D1–D0 R/W 00 00: CODEC_CLKIN = MCLK (device pin)
01: CODEC_CLKIN = BCLK (device pin)
10: Reserved. Do not use.
11: CODEC_CLKIN = PLL_CLK (generated on-chip)
(1) Refer to Figure 31 for more details on clock generation multiplexing and dividers.
Page 0 / Register 5: PLL P and R-VAL
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7 R/W 0 0: PLL is powered down.
1: PLL is powered up.
D6–D4 R/W 001 000: PLL divider P = 8
001: PLL divider P = 1
010: PLL divider P = 2
...
110: PLL divider P = 6
111: PLL divider P = 7
D3–D0 R/W 0001 0000: PLL multiplier R = 16
0001: PLL multiplier R = 1
0010: PLL multiplier R = 2
...
1110: PLL multiplier R = 14
1111: PLL multiplier R = 15
Page 0 / Register 6: PLL J-VAL
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 Reserved. Write only zeros to these bits.
D5–D0 R/W 00 0100 00 0000: Don’t use (reserved)
00 0001: PLL multiplier J = 1
00 0010: PLL multiplier J = 2
00 0011: PLL multiplier J = 3
00 0100: PLL multiplier J = 4 (default)
...
11 1110: PLL multiplier J = 62
11 1111: PLL multiplier J = 63
Page 0 / Register 7: PLL D-VAL MSB
(1)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D6 R/W 00 Reserved. Write only zeros to these bits.
D5–D0 R/W 00 0000 PLL fractional multiplier bits D13–D8
(1) Page 0 / register 7 is updated when page 0 / register 8 is written immediately after page 0 / register 7 is written.
Page 0 / Register 8: PLL D-VAL LSB
(1)
READ/ RESET
BIT DESCRIPTION
WRITE VALUE
D7–D0 R/W 0000 0000 PLL fractional multiplier bits D7–D0
(1) Page 0 / register 8 must be written immediately after writing to page 0 / register 7.
Copyright © 2008–2011, Texas Instruments Incorporated 47