Datasheet

TLV320ADC3001
SLAS548C –OCTOBER 2008– REVISED APRIL 2011 www.ti.com
Table 13. Page / Register Map
PAGE 0: (Clock Multipliers and Dividers, Serial Interfaces, Flags, Interrupts, and Programming ofGPIOs)
Register No. Register Name
0 Page control register
1 S/W RESET
2 Reserved
3 Reserved
4 Clock-gen muxing
5 PLL P and R-VAL
6 PLL J-VAL
7 PLL D-VAL MSB
8 PLL D-VAL LSB
9–17 Reserved
18 ADC NADC clock divider
19 ADC MADC clock divider
20 ADC AOSR
21 ADC IADC
22 ADC miniDSP engine decimation
23 and 24 Reserved
25 CLKOUT MUX
26 CLKOUT M divider
27 ADC interface control 1
28 DATA slot offset programmability 1 (Ch_Offset_1)
29 ADC interface control 2
30 BCLK N divider
31–33 Reserved
34 I
2
S sync
35 Reserved
36 ADC flag register
37 Data slot offset programmability 2 (Ch_Offset_2)
38 I
2
S TDM control register
39–41 Reserved
42 Interrupt flags (overflow)
43 Interrupt flags (overflow)
44 Reserved
45 Interrupt flags-ADC
46 Reserved
47 Interrupt flags-ADC
48–52 Reserved
53 DOUT (Out pin) Control
54–56 Reserved
57 ADC sync control 1
58 ADC sync control 2
59 ADC CIC filter gain control
60 Reserved
61 ADC processing block / miniDSP selection
62 Programmable instruction-mode control bits
63–80 Reserved
44 Copyright © 2008–2011, Texas Instruments Incorporated