Datasheet

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TLV320ADC3001

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SLAS548C –OCTOBER 2008– REVISED APRIL 2011

Based on the available master clock, the chosen AOSR and the targeted sampling rate, the clock divider values

NADC and MADC can be determined. If necessary, the internal PLL can add a large degree of flexibility.

In summary, CODEC_CLKIN (derived directly from the system clock source or from the internal PLL) divided by

MADC, NADC, and AOSR must be equal to the ADC sampling rate ADC_f

. The CODEC_CLKIN clock signal is

shared with the DAC clock-generation block.

CODEC_CLKIN = NADC × MADC × AOSR × ADC_f

To a large degree, NADC and MADC can be chosen independently in the range of 1 to 128. In general, NADC

should be as large as possible as long as the following condition can still be met:

MADC × AOSR / 32 ≥ RC

RC is a function of the chosen processing block and is listed in the Resource Class column of Table 6 .

The common-mode voltage setting of the device is determined by the available analog power supply.

At this point, the following device-specific parameters are known: PRB_Rx, AOSR, NADC, MADC, input and

output common-mode values. If the PLL is used, the PLL parameters P, J, D, and R are determined as well.

Step 2

Setting up the device via register programming:

The following list gives a sequence of items that must be executed in the time between powering the device up

and reading data from the device:

1. Define starting point:

(a) Power up applicable external hardware power supplies

(b) Set register page to 0

2. Program clock settings

(a) Program PLL clock dividers P, J, D, and R (if PLL is used)

(b) Power up PLL (if PLL is used)

(d) Program and power up MADC

(e) Program OSR value

(f) Program I

S word length if required (e.g., 20 bits)

(g) Program the processing block to be used

3. Program analog blocks

(a) Set register page to 1

(b) Program MICBIAS if applicable

(d) Program routing of inputs/common mode to ADC input

(e) Unmute analog PGAs and set analog gain

4. Program ADC

(a) Set register page to 0

(b) Power up ADC channel

A detailed example can be found in Example Register Setup to Record Analog Data Through ADC to Digital Out.

Example Register Setup to Record Analog Data Through ADC to Digital Out

A typical EVM I

C register control script follows to show how to set up the TLV320ADC3001 in record mode with

= 44.1 kHz and MCLK = 11.2896 MHz.

# Key: w 30 XX YY ==> write to I2C address 0x30, to register 0xXX, data 0xYY

# # ==> comment delimiter

# The following list gives an example sequence of items that must be executed in the time

# between powering the device up and reading data from the device. Note that there are

# other valid sequences depending on which features are used.