Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsData collecting ICsData acquisition IC - ADC 16 Bit DSBGA 16

LD(n) LD (n+1)

2 1

3 03

2 1

RD(n)

LEFT CHANNEL RIGHT CHANNEL

WORD

CLOCK

BIT

CLOCK

DATA

n-1 n-2

n-3

n-1 n-2

n-3

n-1 n-2

n-3

Ch_Offset_1 = 0

RD(n) RD(n+1)

2 1

3 03

2 1

LD(n)

RIGHT CHANNEL LEFT CHANNEL

WORD

CLOCK

BIT

CLOCK

DATA

n-1 n-2 n-3 n-1 n-2 n-3 n-1 n-2 n-3

Ch_Offset_1 = 0 Ch_Offset_2 = 3

RD(n) RD(n+1)

2 1

3 03

2 1

LD(n)

RIGHT CHANNEL LEFT CHANNEL

WORD

CLOCK

BIT

CLOCK

DATA

n-1 n-2 n-3 n-1 n-2 n-3 n-1 n-2 n-3

Ch_Offset_1 = 0 Ch_Offset_2 = 3

TLV320ADC3001

SLAS548C –OCTOBER 2008– REVISED APRIL 2011

www.ti.com

Figure 28. DSP Mode With Ch_Offset_1 = 0, Bit Clock Inverted

For DSP mode, the number of bit clocks per frame should be greater than twice the programmed word length of

the data. Also, the programmed offset value should be less than the number of bit clocks per frame by at least

the programmed word length of the data.

Figure 29 shows the DSP time-slot-based mode without channel swapping, and with Ch_Offset_1 = 0 and

Ch_Offset_2 = 3. The MSB of left channel data is valid on the first falling edge of the bit clock after the rising

edge of the word clock. Because the right channel has an offset of 3, the MSB of its data is valid on the third

falling edge of the bit clock after the LSB of the left-channel data. As in the case of other modes, the serial output

bus is put in the high-impedance state, if Hi-Z state operation of the output is enabled, during all the extra

bit-clock cycles in the frame.

Figure 29. DSP Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 3

Figure 30 shows the timing diagram for the DSP mode with left and right channels swapped, Ch_Offset_1 = 0,

and Ch_Offset_2 = 3. The MSB of the right channel is valid on the first falling edge of the bit clock after the rising

edge of the word clock. And, the MSB of the left channel is valid three bit-clock cycles after the LSB of right

channel, because the offset for the left channel is 3.

Figure 30. DSP Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 3, Channel Swap

Enabled