Datasheet

LD(n) LD(n+1)
2 1
0
3
2 1
0
3 3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel Data RD(n) = nth Sample of Right-Channel Data
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2
n-3
n-1 n-2
n-3
n-1 n-2
n-3
Ch_Offset_1 = 0 Ch_Offset_1 = 0
LD(n) LD(n+1)
2 1
0
3 03
2 1
3
RD(n)
LEFTCHANNEL RIGHTCHANNEL
LD(n)=n'thsampleofleftchanneldate RD(n)=n'thsampleofrightchanneldate
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2 n-3 n-1 n-2 n-3 n-1 n-2 n-3
LD(n)
LD(n+1)
2 1
0
3 03
2 1
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel DatA RD(n) = nth Sample of Right-Channel Data
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2
n-3
n-1 n-2
n-3
n-1 n-2
n-3
Ch_Offset_1 = 1
TLV320ADC3001
www.ti.com SLAS548C –OCTOBER 2008– REVISED APRIL 2011
Figure 25 shows the I
2
S mode timing with Ch_Offset_1 = 0 and bit clock inverted.
Figure 25. I
2
S Mode With Ch_Offset_1 = 0, Bit Clock Inverted
For I
2
S mode, the number of bit clocks per channel should be greater than or equal to the programmed word
length of the data. Also, the programmed offset value should be less than the number of bit clocks per frame by
at least the programmed word length of the data.
DSP Mode
In DSP mode, the rising edge of the word clock starts the data transfer with the left-channel data first and is
immediately followed by the right-channel data. Each data bit is valid on the falling edge of the bit clock.
Figure 26 shows the standard timing for the DSP mode.
Figure 26. DSP Mode (Standard Timing)
Figure 27 shows the DSP mode timing with Ch_Offset_1 = 1.
Figure 27. DSP Mode With Ch_Offset_1 = 1
Figure 28 shows the DSP mode timing with Ch_Offset_1 = 0 and bit clock inverted.
Copyright © 2008–2011, Texas Instruments Incorporated 21