Datasheet

RD(n)
RD(n+1)
2 1
03
2 1
03
LD (n)
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2
n-3
n-1 n-2
n-3
n-1 n-2
n-3
Right Channel Left Channel
Ch_Offset_1 = 0 Ch_Offset_2 = 1
LD(n) LD(n+1)
2 1
0
3
2 1
0
3 3
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel Data RD(n) = nth Sample of Right-Channel Data
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-2
n-3
n-1 n-2
n-3
n-1 n-2
n-3
Ch_Offset_1 = 0 Ch_Offset_1 = 0
LD(n) LD(n+1)
4
3
2
5
1
0
4
3
2
5
1
0
5
RD(n)
LEFT CHANNEL RIGHT CHANNEL
LD(n) = nth Sample of Left-Channel Data RD(n) = nth Sample of Right-Channel Data
WORD
CLOCK
BIT
CLOCK
DATA
n-1 n-1 n-1
Ch_Offset_1 = 2 Ch_Offset_1 = 2
TLV320ADC3001
SLAS548C –OCTOBER 2008– REVISED APRIL 2011 www.ti.com
MSB of the left channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the
right channel. Figure 22 shows the operation in this mode with Ch_Offset_1 = 0 and Ch_Offset_2 = 1. The MSB
of the right channel is valid on the first rising edge of the bit clock after the rising edge of the word clock. Data
transfer for the left channel starts following the completion of data transfer for the right channel without waiting for
the falling edge of the word clock. The MSB of the left channel is valid on the second rising edge of the bit clock
after the LSB of the right channel.
Figure 22. Left-Justified Mode, Time-Slot-Based Mode Enabled, Ch_Offset_1 = 0, Ch_Offset_2 = 1,
Channel Swapping Enabled
I
2
S Mode
In I
2
S mode, the MSB of the left channel is valid on the second rising edge of the bit clock after the falling edge
of the word clock. Similarly, the MSB of the right channel is valid on the second rising edge of the bit clock after
the rising edge of the word clock. Figure 23 shows the standard I
2
S timing.
Figure 23. I
2
S Mode (Standard Timing)
Figure 24 shows the I
2
S mode timing with Ch_Offset_1 = 2.
Figure 24. I
2
S Mode With Ch_Offset_1 = 2
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