Datasheet

PGA
0 dB to 40 dB
0.5-dB steps
ADC
AGC
DVDD
DVSS
IOVDD
AVDD
AVSS
Current Bias/
Reference
Audio Clock
Generation
PLL
MCLK
I
2
C Serial
Control Bus
SCL
SDA
I
2
S
TDM
Serial
Bus
Interface
DOUT
BCLK
WCLK
TLV320ADC3001
IN1L(P)
All stages: 0, –6 dB, or Off
by Register Setting
IN1R(M)
Analog
Signal
Input
Switching
MICBIAS
Mic
Bias
IN2L
ADC
AGC
miniDSP
Processing
Blocks
RESET
PGA
0 dB to 40 dB
0.5-dB steps
TLV320ADC3001
SLAS548C –OCTOBER 2008– REVISED APRIL 2011 www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
SIMPLIFIED BLOCK DIAGRAMS
Figure 1. TLV320ADC3001 Block Diagram
2 Copyright © 2008–2011, Texas Instruments Incorporated