Datasheet
TLV320ADC3001
IN2 L
IN1 L(P)
MICBIAS
AVDD
AVSS
DVDD
DVSS
IOVDD
1.65 V–1.95 V
IOVDD
(1.1 V–3.3 V)
A
AVDD
(2.6 V–3.6 V)
SDA
SCL
IOVDD
MCLK
BCLK
WCLK
DOUT
DBB
IN1 R(M)
A
A
D
RESET
R
P
R
P
1mF
0.1
Fm
1 Fm
0.1
Fm
1 Fm
0.1
Fm
1 Fm
1 Fm
1 Fm
2 kW
2 kW
1 Fm
TLV320ADC3001
www.ti.com
SLAS548C –OCTOBER 2008– REVISED APRIL 2011
TYPICAL CIRCUIT CONFIGURATION
Figure 11. Typical Connections
OVERVIEW
The TLV320ADC3001 is a flexible, low-power, stereo audio ADC product with extensive feature integration,
intended for applications in smartphones, PDAs, and portable computing, communication, and entertainment
applications. The product integrates a host of features to reduce cost, board space, and power consumption in
space-constrained, battery-powered, portable applications.
The TLV320ADC3001 consists of the following blocks:
• Stereo audio multibit delta-sigma ADC (8 kHz–96 kHz)
• miniDSP for custom processing
• Built-in processing blocks for selectable digital audio effects (3-D, bass, treble, midrange, EQ, de-emphasis)
• Register configurable combinations of up to three single-ended or one differential and one single-ended audio
inputs
• Fully programmable PLL with extensive ADC clock source and divider options for maximum end-system
design flexibility
• 16-ball wafer chip-scale package (YZH)
Communication to the TLV320ADC3001 for control is via a two-wire I
2
C interface. The I
2
C interface supports
both standard and fast communication modes.
HARDWARE RESET
The TLV320ADC3001 requires a hardware reset after power up for proper operation. After all power supplies are
at their specified values, the RESET pin must be driven low for at least 10 ns. If this reset sequence is not
performed, the TLV320ADC3001 may not respond properly to register reads/writes.
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