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TLV320ADC3001

www.ti.com

SLAS548C –OCTOBER 2008– REVISED APRIL 2011

Low-Power Stereo ADC With Embedded miniDSP

for Wireless Handsets and Portable Audio

Check for Samples: TLV320ADC3001

FEATURES

• 2,24-mm × 2,16-mm NanoFree™ 16-Ball

16-YZH Wafer Chip Scale Package (WCSP)

234

• Stereo Audio ADC

– 92-dBA Signal-to-Noise Ratio

APPLICATIONS

– Supports ADC Sample Rates From 8 kHz to

• Wireless Handsets

96 kHz

• Portable Low-Power Audio Systems

• Instruction-Programmable Embedded miniDSP

• Noise Cancellation Systems

• Flexible Digital Filtering With RAM

• Front-End Voice or Audio Processor for Digital

Programmable Coefficient, Instructions, and

Audio

Built-In Standard Modes

– Low-Latency IIR Filters for Voice

DESCRIPTION

– Linear Phase FIR Filters for Audio

The TLV320ADC3001 is a low-power, stereo audio

– Additional Programmable IIR Filters for EQ,

analog-to-digital converter (ADC) supporting sampling

Noise Cancellation, or Reduction

rates from 8 kHz to 96 kHz with an integrated

programmable-gain amplifier providing up to 40 dB

– Up to 128 Programmable ADC Digital Filter

analog gain or AGC. A programmable miniDSP is

Coefficients

provided for custom audio processing. Front-end

• Three Audio Inputs With Configurable

input coarse attenuation of 0 dB, –6 dB, or off, is also

Automatic Gain Control (AGC)

provided. The inputs are programmable in a

– Programmable in Single-Ended or Fully

combination of single-ended or fully differential

configurations. Extensive register-based power

Differential Configurations

control is available via I

C, enabling mono or stereo

– Can Be Driven Hi-Z for Easy Interoperability

recording. Low power consumption makes the

With Other Audio ICs

TLV320ADC3001 ideal for battery-powered portable

• Low Power Consumption and Extensive

equipment.

Modular Power Control:

The AGC programs to a wide range of attack

– 6-mW Mono Record 8-kHz

(7 ms–1.4 s) and decay (50 ms–22.4 s) times. A

– 11-mW Stereo Record, 8-kHz

programmable noise gate function is included to

avoid noise pumping. Low-latency IIR filters optimized

– 10-mW Mono Record, 48-kHz

for voice and telephony are available, as well as

– 17-mW Stereo Record, 48-kHz

linear-phase FIR filters optimized for audio.

• Programmable Microphone Bias

Programmable IIR filters are also available and may

be used for sound equalization, or to remove noise

• Programmable PLL for Clock Generation

components. The audio serial bus can be

• I

C™ Control Bus

programmed to support I

S, left-justified,

• Audio Serial Data Bus Supports I

right-justified, DSP, PCM, and TDM modes. The

Left/Right-Justified, DSP, PCM, and TDM

audio bus may be operated in either master or slave

Modes

mode.

• Power Supplies:

A programmable integrated PLL is included for

flexible clock generation and support for all standard

– Analog: 2.6 V–3.6 V.

audio rates from a wide range of available MCLKs,

– Digital: Core: 1.65 V–1.95 V,

varying from 512 kHz to 50 MHz, including the most

I/O: 1.1 V–3.6 V

popular cases of 12-MHz, 13-MHz, 16-MHz,

19.2-MHz, and 19.68-MHz system clocks.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2NanoFree, PurePath Studio are trademarks of Texas Instruments.

C is a trademark of NXP B.V.

4All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (81 pages)

PAGE 1
TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 1. PACKAGING/ORDERING INFORMATION PRODUCT PACKAGE (1) PACKAGE DESIGNATOR OPERATING TEMPERATURE RANGE TLV320ADC3001 WSCP-16 YZH –40°C to 85°C (1) ORDERING NUMBER TRANSPORT MEDIA, QUANTITY TLV320ADC3001IYZHT Tape and reel, 250 TLV320ADC3001IYZHR Tape and reel, 3000 For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI Web site at www.ti.com.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) TJ Max (2) VALUE UNIT AVDD to AVSS –0.3 to 3.9 V IOVDD to DVSS –0.3 to 3.9 V DVDD to DVSS –0.3 to 2.5 V Digital input voltage to DVSS –0.3 V to IOVDD + 0.3 V Analog input voltage to AVSS –0.3 V to AVDD + 0.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS At 25°C, AVDD = 3.3 V, IOVDD = 1.8 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT AUDIO ADC THD Input signal level (0-dB) Single-ended input 0.707 Vrms Input common-mode voltage Single-ended input 1.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At 25°C, AVDD = 3.3 V, IOVDD = 1.8 V, DVDD = 1.8 V, fS = 48-kHz, 16-bit audio data (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP 2.25 2.5 MAX UNIT MICROPHONE BIAS 2 Bias voltage Programmable settings, load = 750 Ω 2.75 V AVDD – 0.2 Current sourcing 2.5 V setting Integrated noise BW = 20 Hz to 20 kHz, A-weighted, 1-µF capacitor between MICBIAS and AGND 4 mA µVr ms 3.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com AUDIO DATA SERIAL INTERFACE TIMING DIAGRAMS All specifications at 25°C, DVDD = 1.8 V WCLK td(WS) tr tf BCLK td(DO-WS) td(DO-BCLK) DOUT PARAMETER IOVDD = 1.8 V MIN MAX IOVDD = 3.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com All specifications at 25°C, DVDD = 1.8 V WCLK td(WS) td(WS) tf tr BCLK td(DO-BCLK) DOUT PARAMETER IOVDD = 1.8 V MIN MAX IOVDD = 3.3 V MIN MAX UNIT td(WS) BCLK/WCLK delay time 25 15 ns td(DO-BCLK) BCLK to DOUT delay time 25 15 ns tr Rise time 20 15 ns tf Fall time 20 15 ns NOTE: All timing specifications are measured at characterization. Figure 3.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com All specifications at 25°C, DVDD = 1.8 V WCLK tS(WS) th(WS) tH(BCLK) tf tr BCLK tL(BCLK) td(DO-WS) td(DO-BCLK) DOUT PARAMETER IOVDD = 1.8 V MIN MAX IOVDD = 3.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com All specifications at 25°C, DVDD = 1.8 V (see NOTE) WCLK th(WS) BCLK th(WS) ts(WS) th(WS) tL(BCLK) tH(BCLK) tf td(DO-BCLK) tr DOUT Note A. Falling edge inside a frame for WCLK is arbitrary inside frame. IOVDD = 1.8 V PARAMETER MIN IOVDD = 3.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) 17 Input-Referred Noise - mVRMS 15 13 11 Left Channel Right Channel 9 7 5 0 5 10 15 20 25 PGA Gain Setting - dB 30 35 40 Figure 7. Input-Referred Noise vs. PGA Gain 0.45 Left Gain Error 0.40 Gain - dB 0.35 0.30 0.25 0.20 Right Gain Error 0.15 0.10 0.05 0 0 10 20 30 40 PGA Gain Setting - dB Figure 8.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Micbias - V TYPICAL CHARACTERISTICS (continued) 3.5 3.4 3.3 3.2 3.1 3 2.9 2.8 2.7 2.6 2.5 2.4 2.3 2.2 2.1 2 1.9 1.8 MICBIAS = AVDD MICBIAS = 2.5 V MICBIAS = 2 V 2.7 2.8 2.9 3 3.1 3.2 3.3 3.4 3.5 3.6 AVDD - V Figure 9. MICBIAS Output Voltage vs AVDD 3.2 MICBIAS=AVDD 3 Micbias - V 2.8 2.6 MICBIAS=2.5V 2.4 2.2 MICBIAS=2.0V 2 1.8 -45 -35 -25 -15 -5 5 15 25 Temp - C 35 45 55 65 75 85 Figure 10.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com TYPICAL CIRCUIT CONFIGURATION IOVDD DBB RP AVDD (2.6 V–3.6 V) DO UT BCLK WCLK MCLK RESET 2 kW SCL MICBIAS SDA RP 1 mF AVDD IN1L(P) AVSS 1mF 0.1 mF 1m F A IOVDD (1.1 V–3.3 V) TLV320ADC3001 A 2 kW 1 mF IOVDD IN1R(M) 1 mF 1.65 V–1.95 V DVDD 0.1 mF A IN2L 0.1 mF 1m F 1mF DVSS D Figure 11.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com PLL START-UP When the PLL is powered on, a start-up delay of approximately 10 ms occurs after the power-up command of the PLL and before the clocks are available to the TLV320ADC3001. This delay is to ensure stable operation of the PLL and clock-divider logic. SOFTWARE POWER DOWN By default, all circuit blocks are powered down following a reset condition.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com After the master issues a START condition, it sends a byte that indicates the slave device with which it is to communicate. This byte is called the address byte. Each device on an I2C bus has a unique 7-bit address to which it responds. (Slaves can also have 10-bit addresses; see the I2C specification for details.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com The audio serial interface on the TLV320ADC3001 has an extensive I/O control to allow for communicating with two independent processors for audio data. The processors can communicate with the device one at a time. This feature is enabled by register programming of the various pin selections.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com 1/fs WCLK Frame Time / 2 BCLK DOUT ‘0’ ‘0’ ‘0’ ‘0’ X R-1 R-2 2 1 0 X DOUT_Tristate Figure 15. First Channel Disabled, Second Channel Enabled, Hi-Z State Enabled The sync signal for the ADC filter is not generated based on the disabled channel. The sync signal for the filter corresponds to the beginning of the earlier of the two channels.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 WORD CLOCK www.ti.com LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA n-1 n-2 n-3 3 2 1 n-1 n-2 n-3 0 3 LD(n) 2 1 0 RD(n) LD(n) = nth Sample of Left-Channel Data n-1 n-2 n-3 LD(n+1) RD(n) = nth Sample of Right-Channel Data Figure 17. Left-Justified Mode (Standard Timing) Figure 18 shows the left-justified mode with Ch_Offset_1 = 1.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com valid on the rising edges of the bit clock. With the time-slot-based channel assignment enabled (page 0 / register 38, bit D0 = 1), the left and right channels have independent offsets (Ch_Offset_1 and Ch_Offset_2). The rising edge of the word clock starts data transfer for the first channel after a delay of its programmed offset (Ch_Offset_1) for this channel.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com MSB of the left channel is valid on the (Ch_Offset_2 + 1)th rising edge of the bit clock following the LSB of the right channel. Figure 22 shows the operation in this mode with Ch_Offset_1 = 0 and Ch_Offset_2 = 1. The MSB of the right channel is valid on the first rising edge of the bit clock after the rising edge of the word clock.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Figure 25 shows the I2S mode timing with Ch_Offset_1 = 0 and bit clock inverted. WORD CLOCK LEFT CHANNEL RIGHT CHANNEL BIT CLOCK 3 n-1 n-2 n-3 DATA 2 1 0 n-1 n-2 n-3 LD(n) 3 2 1 0 RD(n) Ch_Offset_1 = 0 3 n-1 n-2 n-3 LD(n+1) Ch_Offset_1 = 0 LD(n) = nth Sample of Left-Channel Data RD(n) = nth Sample of Right-Channel Data Figure 25.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 WORD CLOCK www.ti.com LEFT CHANNEL RIGHT CHANNEL BIT CLOCK DATA n-1 n-2 n-3 3 2 0 n-1 n-2 n-3 1 LD(n) 3 2 1 n-1 n-2 n-3 0 RD(n) 3 LD (n+1) Ch_Offset_1 = 0 Figure 28. DSP Mode With Ch_Offset_1 = 0, Bit Clock Inverted For DSP mode, the number of bit clocks per frame should be greater than twice the programmed word length of the data.
PAGE 23
TLV320ADC3001 www.ti.com SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 AUDIO DATA CONVERTERS The TLV320ADC3001 supports the following standard audio sampling rates: 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, and 96 kHz. The converters can also operate at different sampling rates in various combinations, which are described further as follows.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com 10 MHz ≤ PLLCLK _IN / P ≤ 20 MHz 80 MHz ≤ PLLCLK _IN × K × R / P ≤ 110 MHz 4 ≤ J ≤ 11 R=1 Example: For MCLK = 12 MHz, fS = 44.1 kHz, NADC = 8, MADC = 2, and AOSR = 128: Select P = 1, R = 1, K = 7.5264, which results in J = 7, D = 5264 Example: For MCLK = 12 MHz, fS = 48 kHz , NADC = 8, MADC = 2, and AOSR = 128: Select P = 1, R = 1, K = 8.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com A detailed diagram of the audio clock section of the TLV320ADC3001 is shown in Figure 31. BCLK MCLK 50 MHz MAX 13 MHzMAX BCLK is an input in slave mode P0:0x1B(27):3 [ADC Interface Control ] (0h) ADC_CLK ADC_MOD_CLK P0:0x04(4) [Clock-Gen Muxing ] (0h) PLL_CLK_IN REG P0:0x1D(29) [ADC Interface Control 2] (2h) PLL_CLKIN 50 MHz MAX PLL x(RxJ.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com STEREO AUDIO ADC The TLV320ADC3001 includes a stereo audio ADC, which uses a delta-sigma modulator with 128-times oversampling in single-rate mode, followed by a digital decimation filter. The ADC supports sampling rates from 8 kHz to 48 kHz in single-rate mode, and up to 96 kHz in dual-rate mode.
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TLV320ADC3001 www.ti.com SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 During volume control changes, the soft-stepping feature is used to avoid audible artifacts. The soft-stepping rate can be set to either 1 or 2 gain steps per sample. Soft-stepping can also be entirely disabled. This soft-stepping is configured via page 0 / register 81, bits D1–D0, and is common to soft-stepping control for the analog PGA.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 • • • • • www.ti.com continuously calculates the energy of the recorded signal. If the calculated energy is less than the set noise threshold, then the AGC does not increase the input gain to achieve the target level.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 3.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com AGC IN1L(P) IN1L(P) IN2L IN2L + IN1R(M) + -- PGA 0/+40 dB 0.5 dB steps ADC IN1L(P) + - IN1R(M) All coarse stage attenuations are set to 0 dB, -6 dB, or Off by register setting. The default is all the switches are off at startup. AGC IN1R(M) IN1R(M) + IN1L(P) + IN1L(P) IN1R(M) -+ - PGA 0/+40 dB 0.5 dB steps ADC Figure 33. TLV320ADC3001 Available Audio Input Path Configurations Table 4.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com the ac-coupling capacitors connected to analog inputs biased up at a normal dc level, thus avoiding the need for them to charge up suddenly when the input is changed from being unselected to selected for connection to an ADC PGA. This option is controlled in page 1 / register 52 through page 1 / register 57.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com The signal processing blocks available are: • First-order IIR • Scalable number of biquad filters • Variable-tap FIR filter • AGC The processing blocks are tuned for common cases and can achieve high anti-alias filtering or low group delay in combination with various signal processing effects such as audio effects and frequency shaping. The available first order IIR, biquad, and FIR filters have fully user-programmable coefficients.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Five Biquads, First-Order IIR, AGC, Filter A From Delta-Sigma Modulator or Digital Microphone Filter A HA HB HC HD st 1 Order IIR x HE AGC Gain Compen sation To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 35.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Three Biquads, First-Order IIR, AGC, Filter B From Delta-Sigma Modulator or Digital Microphone Filter B HA HC HB AGC Gain Compen sation 1stOrder IIR x To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 38.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Five Biquads, First-Order IIR, AGC, Filter C From Delta-Sigma Modulator or Digital Microphone Filter C HA HB HC HD HE st 1 Order IIR x AGC Gain Compen sation To Audio Interface AGC From Digital Vol. Ctrl To Analog PGA Figure 41.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Biquad Section The transfer function of each of the biquad filters is given by Equation 3. N0 + 2 × N1z -1 + N2 z -2 H(z) = 215 - 2 ´ D1z -1 - D2 z -2 (3) The frequency response for each of the biquad sections with default coefficients is flat at a gain of 0 dB. Table 8.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 9.
PAGE 38
TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Decimation Filter A This filter is intended for use at sampling rates up to 48 kHz. When configuring this filter, the oversampling ratio of the ADC can either be 128 or 64. For highest performance, the oversampling ratio must be set to 128. Filter A can also be used for 96 kHz at an AOSR of 64. Table 10. ADC Decimation Filter A, Specification Parameter Condition Value (Typical) Unit AOSR = 128 Filter gain pass band 0…0.39 fS 0.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Decimation Filter B Filter B is intended to support sampling rates up to 96kHz at a oversampling ratio of 64. Table 11. ADC Decimation Filter B, Specifications Parameter Condition Value (Typical) Units AOSR = 64 Filter gain pass band 0…0.39 fS ±0.077 dB Filter gain stop band 0.60 fS…32 fS –46 dB 11/fS Sec. Filter group delay Pass-band ripple, 8 ksps 0…0.39 fS 0.076 dB Pass-band ripple, 44.18 ksps 0…0.39 fS 0.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Decimation Filter C Filter type C along with AOSR of 32 is specially designed for 192ksps operation for the ADC. The pass band which extends up to 0.11 × fS (corresponds to 21 kHz), is suited for audio applications. Table 12. ADC Decimation Filter C, Specifications Parameter Condition Value (Typical) Units Filter gain from 0 to 0.11 fS 0…0.11 fS ±0.033 dB Filter gain from 0.28 fS to 16 fS 0.
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TLV320ADC3001 www.ti.com SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 Based on the available master clock, the chosen AOSR and the targeted sampling rate, the clock divider values NADC and MADC can be determined. If necessary, the internal PLL can add a large degree of flexibility. In summary, CODEC_CLKIN (derived directly from the system clock source or from the internal PLL) divided by MADC, NADC, and AOSR must be equal to the ADC sampling rate ADC_fS.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com # ADC3101EVM Key Jumper Settings and Audio Connections: # 1. Remove Jumpers W12 and W13 # 2. Insert Jumpers W4 and W5 # 3. Insert a 3.5mm stereo audio plug into J9 for # single-ended input IN1L(P) - left channel and # single-ended input IN1R(M) - right channel ################################################################ # 1.
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TLV320ADC3001 www.ti.com # w # # # # # w # # w # # # # # w # # # # w # # # # w # SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 Right Analog PGA Seeting = 0dB 30 3c 00 (d) Routing of inputs/common mode to ADC input (e) Unmute analog PGAs and set analog gain Left ADC Input selection for Left PGA = IN1L(P) as Single-Ended 30 34 fc Right ADC Input selection for Right PGA = IN1R(M) as Single-Ended 30 37 fc 4.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 13. Page / Register Map PAGE 0: (Clock Register No.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 13. Page / Register Map (continued) 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102–127 Reg No.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 13. Page / Register Map (continued) ADC Digital Filter RAM and Instruction Pages: PAGE 4: ADC Programmable Coefficients RAM (1:63) PAGE 5: ADC Programmable Coefficients RAM (65:127) PAGE 6–PAGE 31: Reserved. Do not read from or write to these pages. PAGE 32–PAGE 47: ADC Programmable Instruction RAM (0:511) Page 32 Instruction Inst(0:31) Page 33 Instruction Inst(32:63) Page 34 Instruction Inst(64:95) ...
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 4: Clock-Gen Multiplexing (1) D7–D4 D3–D2 READ/ WRITE R R/W RESET VALUE 0000 00 D1–D0 R/W 00 BIT (1) DESCRIPTION Reserved. Do not write any value other than reset value. 00: PLL_CLKIN = MCLK (device pin) 01: PLL_CLKIN = BCLK (device pin) 10: Reserved. Do not use. 11: PLL_CLKIN = logic level 0 00: CODEC_CLKIN = MCLK (device pin) 01: CODEC_CLKIN = BCLK (device pin) 10: Reserved. Do not use.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 9 Through Page 0 / Register 17: Reserved BIT READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0001 BIT D7 READ/ WRITE R/W RESET VALUE 0 D6–D0 R/W 000 0001 D7–D0 DESCRIPTION Reserved. Do not write to these registers.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 22: ADC miniDSP Engine Decimation BIT D7–D4 D3–D0 READ/ WRITE R R/W RESET VALUE 0000 0100 DESCRIPTION Reserved. Do not write any value other than reset value. 0000: Decimation ratio in ADC miniDSP engine = 16 0001: Decimation ratio in ADC miniDSP engine = 1 0010: Decimation ratio in ADC miniDSP engine = 2 ...
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 28: Data Slot Offset Programmability 1 (Ch_Offset_1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: 0000 0010: ... 1111 1110: 1111 1111: Offset = 0 BCLKs. Offset is measured with respect to WCLK rising edge in DSP mode.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 35: Reserved READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R RESET VALUE 0 D6 R 0 D5 (1) R 0 D4 D3 R R 0 0 D2 R 0 D1 (1) R 0 D0 R 0 BIT D7–D0 DESCRIPTION Reserved. Do not write to this register.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 42: Interrupt Sticky Flags (Overflow) D7–D4 D3 (1) READ/ WRITE R R RESET VALUE 0000 0 D2 (1) R 0 D1 (1) R 0 D0 R 0 BIT (1) DESCRIPTION Reserved Left ADC Overflow Flag 0: No overflow in left ADC 1: Overflow has occurred in left ADC since last read of this register. Right ADC Overflow Flag 0: No overflow in right ADC 1: Overflow has occurred in right ADC since last read of this register.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 58: ADC Sync Control 2 BIT D7–D0 READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: 0000 0010: ...
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 63 Through Page 0 / Register 80: Reserved BIT READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 0 D6 R/W 0 D5–D2 D1–D0 R/W R/W 0000 00 D7 READ/ WRITE R/W RESET VALUE 1 D6–D4 R/W 000 D3 R/W 1 D2–D0 R/W 000 READ/ WRITE R R/W RESET VALUE (1) 0 000 0000 D7–D0 DESCRIPTION Reserved. Do not write to these registers.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 84: Right ADC Volume Control BIT D7 D6–D0 (1) READ/ WRITE R R/W RESET VALUE (1) 0 000 0000 DESCRIPTION Reserved. Do not write any value other than reset value. 100 0000–110 1000: Right ADC channel volume = 0 dB 110 1000: Rght ADC channel volume = –12 dB 110 1001: Right ADC channel volume = –11.5 dB 110 1010: Rght ADC channel volume = –11 dB ... 111 1111: Right ADC channel volume = –0.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 91: Left AGC Noise Debounce BIT D7–D5 D4–D0 READ/ WRITE R R/W RESET VALUE 000 0 0000 READ/ WRITE R R/W RESET VALUE 0000 0000 READ/ WRITE R RESET VALUE 0000 0000 DESCRIPTION Reserved. Do not write any value other than reset value.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 94: Right AGC Control 1 D7 READ/ WRITE R/W RESET VALUE 0 D6–D4 R/W 000 D3–D0 R 0000 D7–D6 READ/ WRITE R/W RESET VALUE 00 D5–D1 R/W 00 000 D0 R/W 0 BIT DESCRIPTION 0: Right AGC disabled 1: Right AGC enabled 000: Right AGC target level = –5.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 98: Right AGC Decay Time D7–D3 READ/ WRITE R/W RESET VALUE 0000 0 D2–D0 R/W 000 BIT DESCRIPTION 0000 0: Right AGC decay time = 1 × (512/fS) 0000 1: Right AGC decay time = 3 × (512/fS) 0001 0: Right AGC decay time = 5 × (512/fS) 0001 1: Right AGC decay time = 7 × (512/fS) 0010 0: Right AGC decay time = 9 × (512/fS) ...
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 0 / Register 101: Right AGC Gain Applied BIT (1) D7–D0 (1) READ/ WRITE R RESET VALUE 0000 0000 DESCRIPTION Right AGC Gain Value Status: 1110 1000: Gain applied by right AGC = –12 dB 1110 1001: Gain applied by right AGC = –11.5 dB ... 1111 1111: Gain applied by right AGC = –0.5 dB 0000 0000: Gain applied by right AGC = 0 dB 0000 0001: Gain applied by right AGC = 0.5 dB ... 0100 1111: Gain applied by right AGC = 39.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 1 / Register 26: Dither Control D7–D4 READ/ WRITE R/W RESET VALUE 0000 D3–D0 R/W 0000 BIT DESCRIPTION DC Offset Into Input of Left ADC; Signed Magnitude Number in ±15-mV Steps 1111: –105 mV ... 1011: –45 mV 1010: –30 mV 1001: –15 mV 0000: 0 mV 0001: 15 mV 0010: 30 mV 0011: 45 mV ... 0111: 105 mV DC Offset Into Input of Right ADC; Signed Magnitude Number in ±15-mV Steps 1111: –105 mV ...
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 1 / Register 53: Reserved READ/ WRITE R RESET VALUE XXXX XXXX D7 D6 READ/ WRITE R/W R/W RESET VALUE 0 0 D5–D4 R/W 11 D3–D2 D1–D0 R/W R/W 11 11 BIT D7–D0 DESCRIPTION Reserved. Do not write to this register. Page 1 / Register 54: Left ADC Input Selection for Left PGA BIT (1) DESCRIPTION Reserved. Do not write any value other than reset value.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Page 1 / Register 58: Reserved BIT READ/ WRITE R RESET VALUE XXXX XXXX D7 READ/ WRITE R/W RESET VALUE 1 D6–D0 R/W 000 0000 D7 READ/ WRITE R/W RESET VALUE 1 D6–D0 R/W 000 0000 D7–D0 DESCRIPTION Reserved. Do not write to this register. Page 1 / Register 59: Left Analog PGA Settings BIT DESCRIPTION 0: Left PGA is not muted. 1: Left PGA is muted. 000 0000: Left PGA gain = 0 dB 000 0001: Left PGA gain = 0.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Control Registers, Page 4: ADC Digital Filter Coefficients Default values shown for this page only become valid 100 μs following a hardware or software reset. Page 4 / Register 0: Page Control Register (1) READ/ WRITE R/W BIT D7–D0 (1) RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 14.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 14.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 14.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 14.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Control Registers, Page 5: ADC Programmable Coefficients RAM (65:127) Page 5 / register 0 is the page control register as desribed following. Page 5 / Register 0: Page Control Register (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ... 1111 1110: 1111 1111: Page 0 selected Page 1 selected Page 254 selected (reserved) Page 255 selected (reserved) Valid pages are 0, 1, 4, 5, and 32–47.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 15.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Table 15.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Control Registers, Page 32: ADC DSP Engine Instruction RAM (0:31) Control registers from page 32 through page 47 contain instruction RAM for the ADC miniDSP. There are 32 instructions / page and 16 pages, so the TLV320ADC3001 miniDSP supports 512 instructions. Page 32 / Register 0: Page Control Register (1) BIT D7–D0 (1) READ/ WRITE R/W RESET VALUE 0000 0000 DESCRIPTION 0000 0000: 0000 0001: ...
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com Control Registers, Page 33 Through Page 47: ADC DSP Engine Instruction RAM (32:63) Through (480:511) The structuring of the registers within page 33 through page 43 is identical to that of page 32. Only the instruction numbers differ. The range of instructions within each page is listed in the following table.
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 www.ti.com REVISION HISTORY Changes from Original (September 2008) to Revision A Page • Changed Figure 5 - DSP Timing in Slave Mode. Added the WCLK text note. .................................................................. 10 • Changed Figure 11 Typical Connections ............................................................................................................................
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TLV320ADC3001 SLAS548C – OCTOBER 2008 – REVISED APRIL 2011 Changes from Revision B (March 2010) to Revision C www.ti.com Page • Changed pinout diagram to top view .................................................................................................................................... 3 • Inserted missing table reference .........................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 28-Sep-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TLV320ADC3001IYZHR DSBGA YZH 16 3000 178.0 8.4 2.18 TLV320ADC3001IYZHR DSBGA YZH 16 3000 180.0 8.4 2.38 TLV320ADC3001IYZHT DSBGA YZH 16 250 178.0 8.4 2.18 TLV320ADC3001IYZHT DSBGA YZH 16 250 180.0 8.4 2.38 2.
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PACKAGE MATERIALS INFORMATION www.ti.com 28-Sep-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV320ADC3001IYZHR DSBGA YZH 16 3000 217.0 193.0 35.0 TLV320ADC3001IYZHR DSBGA YZH 16 3000 182.0 182.0 17.0 TLV320ADC3001IYZHT DSBGA YZH 16 250 217.0 193.0 35.0 TLV320ADC3001IYZHT DSBGA YZH 16 250 182.0 182.0 17.
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D: Max = 2.271 mm, Min = 2.21 mm E: Max = 2.19 mm, Min = 2.
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