Datasheet

      
      
  ! !
SLOS245E − MARCH 2000 − REVISED JANUARY 2005
17
WWW.TI.COM
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim Parts Release 9.1, the model generation
software used with Microsim PSpice. The Boyle macromodel (see Note 2) and subcircuit in Figure 35 are
generated using TLV278x typical electrical and operating characteristics at T
A
= 25°C. Using this information,
output simulations of the following key parameters can be generated to a tolerance of 20% (in most cases):
D Maximum positive output voltage swing
D Maximum negative output voltage swing
D Slew rate
D Quiescent power dissipation
D Input bias current
D Open-loop voltage amplification
D Unity-gain frequency
D Common-mode rejection ratio
D Phase margin
D DC output resistance
D AC output resistance
D Short-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers,” IEEE Journal
of Solid-State Circuits, SC-9, 353 (1974).
* TLV2782_HVDD operational amplifier ”macromodel” subcircuit
* created using Model Editor release 9.1 on 03/3/00 at 9:47
* Model Editor is an OrCAD product.
*
* connections: non−inverting input
* | inverting input
* | | positive power supply
* | | | negative power supply
* | | | | output
* | | | | |
.subckt TLV2782_HVDD 1 2 3 4 5
*
c1 11 12 49.58E−15
c2 6 7 10.200E−12
css 10 99 1.0000E−30
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 4 3 dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0
41.096E6 −1E3 1E3 41E6
−41E6
ga 6 0 11 12 544.75E−6
gcm 0 6 10 99 1.1538E−9
iss 10 4 dc 56.957E−6
hlim 90 0 vlim 1K
j1 11 2 10 jx1
J2 12 1 10 jx2
r2 6 9 100.00E3
rd1 3 11 1.8357E3
rd2 3 12 1.8357E3
ro1 8 5 10
ro2 7 99 10
rp 3 4 2.1845E3
rss 10 99 3.5114E6
vb 9 0 dc 0
vc 3 53 dc .81911
ve 54 4 dc .81911
vlim 7 8 dc 0
vlp 91 0 dc 45.400
vln 0 92 dc 45.400
.model dx D(Is=800.00E−18)
.model dy D(Is=800.00E−18 Rs=1m Cjo=10p)
.model jx1 NJF(Is=500.00E−15 Beta=5.2102E−3 Vto=−1)
.model jx2 NJF(Is=500.00E−15 Beta=5.2102E−3 Vto=−1)
.ends
IN−
G
D
S
D
S
G
rp
IN+
rd1 rd2
rss
egnd
fb
ro2
ro1
vlim
OUT
ga
ioffgcm
vb
c1
dc
iss
dp
GND
V
DD
css
c2
ve
de
dlp dln
vlnhlimvlp
10
4
1
11 12
3
53
54
96
8
5
7
91 90 92
vc
99
+
+
+
+
+
+
+
−
−
−
−
−−
−
−
+
r2
2
Figure 35. Boyle Macromodel and Subcircuit
PSpice and Parts are trademarks of MicroSim Corporation.