Datasheet

TIMING CHARACTERISTICS
(1)
TLV2556-EP
www.ti.com ................................................................................................................................................... SLAS598A – NOVEMBER 2008 – REVISED JULY 2009
operating characteristics, V
REF+
= 2.5 V, SCLK frequency = 10 MHz, V
CC
= 2.7 V, load = 25 pF, T
A
= -40 ° C to 85 ° C (unless
otherwise noted)
PARAMETER MIN TYP MAX UNIT
t
w1
Pulse duration I/O CLOCK high or low 40 100000 ns
t
su1
Setup time DATA IN valid before I/O CLOCK rising edge (see Figure 38 ) 22 ns
t
h1
Hold time DATA IN valid after I/O CLOCK rising edge (see Figure 38 ) 0 ns
t
su2
Setup time CS low before 1st rising I/O CLOCK edge
(2)
(see Figure 39 ) 33 ns
t
h2
Hold time CS pulse duration high time (see Figure 39 ) 100 ns
t
h3
Hold time CS low after last I/O CLOCK falling edge (see Figure 39 ) 0 ns
t
h4
Hold time DATA OUT valid after I/O CLOCK falling edge (see Figure 40 ) 2 ns
t
h5
Hold time CS high after EOC rising edge when CS is toggled (see Figure 43 ) 0 ns
t
h6
Hold time CS high after INT falling edge (see Figure 43 ) 0 ns
Hold time I/O CLOCK low after EOC rising edge or INT falling edge when CS is held
t
h7
10 ns
low (see Figure 44 )
Load = 25 pF 30
Delay time CS falling edge to DATA OUT valid
t
d1
ns
(MSB or LSB) (see Figure 37 )
Load = 10 pF 22
t
d2
Delay time CS rising edge to DATA OUT high impedance (see Figure 37 ) 10 ns
t
d3
Delay time I/O CLOCK falling edge to next DATA OUT bit valid (see Figure 40 ) 2 33 ns
t
d4
Delay time last I/O CLOCK falling edge to EOC falling edge (see Figure 41 ) 75 ns
t
d5
Delay time last I/O CLOCK falling edge to CS falling edge to abort conversion 1.5 µ s
t
d6
Delay time last I/O CLOCK falling edge to INT falling edge (see Figure 41 ) MAX(t
conv
) ns
Delay time EOC rising edge or INT falling edge to DATA OUT valid: MSB or LSB first
t
d7
20 ns
(see Figure 42 )
t
d9
Delay time I/O CLOCK high to INT rising edge when CS is held low (see Figure 44 ) 1 55 ns
t
t1
Transition time I/O CLOCK
(2)
(see Figure 40 ) 1 µ s
t
t2
Transition time DATA OUT (see Figure 40 ) 5 ns
t
t3
Transition time INT/EOC, CL = 7 pF (see Figure 41 and Figure 42 ) 4 ns
t
t4
Transition time DATA IN, CS 10 µ s
MAX(t
conv
) +
t
cyc
Total cycle time (sample, conversion and delays)
(2)
I/O period µ s
(8/12/16 CLKs)
Source impedance = 25 Ω 800
Source impedance = 100 Ω 850
t
sample
Channel acquisition time (sample), at 1 k Ω
(2)
ns
Source impedance = 500 Ω 1000
Source impedance = 1 k Ω 1600
(1) Timing parameters are not production tested.
(2) I/O CLOCK period = 8x [1/(I/O CLOCK frequency)] or 12x [1/(I/O CLOCK frequency)] or 16x [1/(I/O CLOCK frequency)] depends on I/O
format selected.
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