Datasheet

Access Cycle Sample Cycle
MSB
DATA OUT
1
2
3
5
4
6 10 11 12
1
I/O CLOCK
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−8 MSB−9 LSB+1 LSB
16
DATA IN
8
7
9
MSB−6 MSB−7
Low Level
MSB
D7
EOC
InitializeInitialize
Shift in New Multiplexer Address, Simultaneously
Shift Out Previous Conversion Result
Previous Conversion Data
Pad Zeros
Channel
Address
Output Data
Format
A/D Conversion Interval
t
conv
DATA IN Can be Tied or Held High
CS
TLV2556-EP
SLAS598A – NOVEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 53. Timing for Default Mode Not Using CS: (16-Clock Transfer, MSB First, External Reference, Pin
19 = EOC, Input = AIN0)
To remove the device from default mode, CFGR2 – D0 must be reset to 0. Valid sample/convert cycles can
resume on the cycle following the CFGR2 configuration.
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