Datasheet

Timing Information
DATA OUT
1
2
3
5
4
6 10 11 12
1
I/O CLOCK
Hi−Z State
DATA IN
8
7
9
D7
16
D3 D2 D1 D0
Configure CFGR1
1st Conversion Cycle
CS
First Cycle After Power-Up: Configure CFGR2
Access Cycle Data Cycle
Invalid Conversion Data
Command 1111 CFGR2 Data
Timing Diagrams
1
2
3
5
4
6 10 11 12
1
MSB−1 MSB−2 MSB−3 MSB−4 MSB−5 MSB−8 MSB−9 LSB+1 LSB
Hi−Z State
2
3
D6 D5 D4 D3 D2 D1 D0 D6 D5D7
8
7
9
MSB−6 MSB−7
D7
Previous Conversion Data
MSB
MSB MSB−2MSB−1
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous Conversion Result
Access
Cycle
Sample Cycle
Channel
Address
A/D Conversion Interval
Output Data
Format
t
conv
CS
I/O
CLOCK
DATA
OUT
DATA
IN
EOC
Initialize Initialize
INT
TLV2556-EP
SLAS598A – NOVEMBER 2008 – REVISED JULY 2009 ................................................................................................................................................... www.ti.com
PARAMETER MEASUREMENT INFORMATION (continued)
Figure 45. Timing for CFGR2 Configuration
The host must configure CFGR2 before valid device conversions can begin. This can be accessed through
command 1111. This can be done using 8, 12, or 16 I/O CLOCK clocks. (A minimum of 8 is required to fully
program CFGR2.)
After CFGR2 is configured, the following cycle configures CFGR1 and a valid sample/conversion is performed.
CS can be held low for each remaining cycle. First valid conversion output data is available on the third cycle
after power up.
A. To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after the CS falling edge before
responding to control input signals. Therefore, no attempt should be made to clock in an address until the minimum
CS setup time has elapsed.
Figure 46. Timing for 12-Clock Transfer Using CS With DATA OUT Set for MSB First
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