Datasheet

TLV2556
SLAS355A – DECEMBER 2001 – REVISED SEPTEMBER 2002
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PRINCIPLES OF OPERATION
conversion cycle
A conversion cycle is started only after the I/O cycle is completed, which minimizes the influence of external
digital noise on the accuracy of the conversion. This cycle is transparent to the user because it is controlled by
an internal clock (oscillator). The total conversion time is equal to 13.5 OSC clocks plus a small delay (~25 ns)
to start the OSC. During the conversion period, the device performs a successive-approximation conversion
on the analog input voltage.
When programmed as EOC, pin 19 goes low at the start of the conversion cycle and goes high when the
conversion is complete and the output data register is latched. After EOC goes low, the analog input can be
changed without affecting the conversion result. Since the delay from the falling edge of the last I/O CLOCK to
the falling edge of EOC is fixed, any time-varying analog input signals can be digitized at a fixed rate without
introducing systematic harmonic distortion or noise due to timing uncertainty.
When programmed as INT
, pin 19 goes low when the conversion is complete and the output data register is
latched. The next I/O CLOCK rising edge clears the INT
output. The time from the last I/O CLOCK falling edge
to the falling INT
edge is equivalent to the EOC delay mentioned above plus the maximum conversion time. INT
is cancelled by (or brought to high) by either the next CS
falling edge or the next SCLK rising edge (when CS
is held low all of the time for multiple cycles). When CS is held low continuously (for multiple cycles) MSB output
occurs after the first rising edge of I/O CLOCK after EOC is inactive or the falling edge of INT
.
power up and initialization
After power up, CS must be taken from high to low to begin an I/O cycle. INT/EOC pin is initially high, and both
configuration registers are set to all zeroes. The contents of the output data register are random, and the first
conversion result should be ignored. To initialize during operation, CS
is taken high and is then returned low
to begin the next I/O cycle. The first conversion after the device has returned from the power-down state may
not read accurately due to internal device settling.
Table 1. Operational Terminology
Current (N) I/O cycle The entire I/O CLOCK sequence that transfers address and control data into the data register and clocks
the digital result from the previous conversion from DATA OUT.
Current (N) conversion cycle The conversion cycle starts immediately after the current I/O cycle. The end of the current I/O cycle is the
last clock falling edge in the I/O CLOCK sequence. The current conversion result is loaded into the out-
put register when conversion is complete.
Current (N) conversion result The current conversion result is serially shifted out on the next I/O cycle.
Previous (N–1) conversion cycle The conversion cycle just prior to the current I/O cycle
Next (N+1) I/O cycle The I/O period that follows the current conversion cycle
Example:
In 12-bit mode, the result of the current conversion cycle is a 12-bit serial-data stream clocked out during the
next I/O cycle. The current I/O cycle must be exactly 12 bits long to maintain synchronization, even when this
corrupts the output data from the previous conversion. The current conversion is begun immediately after the
twelfth falling edge of the current I/O cycle.