Datasheet

TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
timing diagrams/conversion cycles (continued)
SCLK
1 2 3 4 5 6 12 13 14 15 16 1
CS
FS
OD9 OD8OD11 OD10 OD7 OD6 OD0
SDO
t
(sample)
t
c
t
(powerdown)
Figure 3. TLV2541 Timing: Control via CS and FS or FS Only
SCLK
2 3 4 5 1 12 16
CS
SDO
t
(powerdown)
t
c
1 4 161241
t
(sample)
>8 SCLKs, MUX Toggles to AIN1
AIN0 Result
t
c
<8 SCLKs, MUX
Resets to AIN0
t
(sample)
OD11 OD0
Figure 4. TLV2542 Reset Timing
OD8
SCLK
1 2 3 4 5 6 12 13 14 15 16
CS
OD7 OD6 OD5 OD0
SDO
t
(sample)
t
c
t
(powerdown)
7
OD9
1
OD10 OD9OD11 OD10
OD11
Figure 5. TLV2542 and TLV2545 Timing
using CS as the FS input
When interfacing the TLV2541 with the TMS320 DSP, the FSR signal from the DSP may be connected to the
CS input if this is the only device on the serial port. This saves one output terminal from the DSP. (Output data
changes on the falling edge of SCLK. This is the default configuration for the TLV2542 and TLV2545.)