Datasheet

TLV2541, TLV2542, TLV2545
2.7-V TO 5.5-V, LOW-POWER, 12-BIT, 140/200 KSPS,
SERIAL ANALOG-TO-DIGITAL CONVERTERS WITH AUTOPOWER DOWN
SLAS245E −MARCH 2000 − REVISED APRIL 2010
4
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
detailed description (continued)
GND/AIN(−)
ADC Code
AIN
Charge
Redistribution
DAC
Control
Logic
_
+
Figure 1. Simplified SAR Circuit
serial interface
OUTPUT DATA FORMAT
MSB LSB
D15−D4 D3−D0
Conversion result (OD11−OD0) Don’t care
The output data format is binary (unipolar straight binary).
binary
Zero-scale code = 000h, Vcode = GND
Full-scale code = FFFh, Vcode = V
REF
− 1 LSB
pseudo-differential inputs
The TLV2545 operates in pseudo-differential mode. The inverted input is available on pin 5. It can have a
maximum input ripple of ±0.2 V. This is normally used for ground noise rejection.
control and timing
start of the cycle
Each cycle may be started by either CS
, FS, or a combination of both. The internal state machine requires one
SCLK high-to-low transition to determine the state of these control signals so internal blocks can be powered
up in an active cycle. Special care to SPI mode is necessary. Make sure there is at least one SCLK whenever
CS
(pin 1) is high to ensure proper operation.
TLV2541
D Control via CS ( FS = 1 at the falling edge of CS)—The falling edge of CS is the start of the cycle. The MSB
should be read on the first falling SCLK edge after CS
is low. Output data changes on the rising edge of
SCLK. This is typically used for a microcontroller with an SPI interface, although it can also be used for a
DSP. The microcontroller SPI interface should be programmed for CPOL = 0 (serial clock referenced to
ground) and CPHA = 1 (data is valid on the falling edge of the serial clock). At least one falling edge transition
on SCLK is needed whenever CS
is brought high.
D Control via FS (CS is tied/held low)—The MSB is presented after the rising edge of FS. The falling edge
of FS is the start of the cycle. The MSB should be read on the first falling edge of SCLK after FS is low. This
is the typical configuration when the ADC is the only device on the DSP serial port.