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PARAMETER MEASUREMENT INFORMATION
_
+
R
NULL
R
L
C
L
APPLICATION INFORMATION
DRIVING A CAPACITIVE LOAD
C
LOAD
R
F
Input
Output
R
G
R
NULL
_
+
OFFSET VOLTAGE
V
OO
+ V
IO
ǒ
1 )
ǒ
R
F
R
G
Ǔ
Ǔ
" I
IB)
R
S
ǒ
1 )
ǒ
R
F
R
G
Ǔ
Ǔ
" I
IB*
R
F
+
−
V
I
+
R
G
R
S
R
F
I
IB−
V
O
I
IB+
TLV2470 , , TLV2471
TLV2472 , TLV2473
TLV2474 , TLV2475 , TLV247xA
SLOS232E – JUNE 1999 – REVISED JULY 2007
Figure 41.
When the amplifier is configured in this manner, capacitive loading directly on the output will decrease the
device phase margin leading to high-frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10pF, it is recommended that a resistor (R
NULL
) be placed in series with the output of the amplifier, as
shown in Figure 42 . A minimum value of 20 Ω should work well for most applications.
Figure 42. Driving a Capacitive Load
The output offset voltage (V
OO
) is the sum of the input offset voltage (V
IO
) and both input bias currents (I
IB
) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset voltage:
Figure 43. Output Offset Voltage Model
15
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