Datasheet

1
0.75
0.5
0
Maximum Power Dissipation (W)
1.25
1.5
1.75
0.25
2
MSOP Package
Low-K Test PCB
θ
JA
= 260°C/W
T
J
= 150°C
PDIP Package
Low-K Test PCB
θ
JA
= 104°C/W
SOIC Package
Low-K Test PCB
θ
JA
= 176°C/W
SOT-23 Package
Low-K Test PCB
θ
JA
= 324°C/W
–40
–25
–55
50 65 80
95
110 125
Free-Air Temperature (, T C)
A
°
–10
5
20 35
( )
MAX A
D
JA
T T
P
q
-
=
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com SGLS008E –MARCH 2003–REVISED OCTOBER 2012
• Proper power supply decoupling − Use a 6.8-μF tantalum capacitor in parallel with a 0.1-μF ceramic capacitor
on each supply terminal. It may be possible to share the tantalum among several amplifiers depending on the
application, but a 0.1-μF ceramic capacitor should always be used on the supply terminal of every amplifier.
In addition, the 0.1-μF capacitor should be placed as close as possible to the supply terminal. As this distance
increases, the inductance in the connecting trace makes the capacitor less effective. The designer should
strive for distances of less than 0.1 inches between the device power terminals and the ceramic capacitors.
• Sockets − Sockets can be used but are not recommended. The additional lead inductance in the socket pins
often leads to stability problems. Surface-mount packages soldered directly to the printed circuit board is the
best implementation.
• Short trace runs/compact part placements − Optimum high performance is achieved when stray series
inductance has been minimized. To realize this, the circuit layout should be made as compact as possible,
thereby minimizing the length of all trace runs. Particular attention should be paid to the inverting input of the
amplifier. Its length should be kept as short as possible. This minimizes stray capacitance at the input of the
amplifier.
• Surface-mount passive components − Using surface-mount passive components is recommended for high-
performance amplifier circuits for several reasons. First, because of the extremely low lead inductance of
surface-mount components, the problem with stray series inductance is greatly reduced. Second, the small
size of surface-mount components naturally leads to a more compact layout, thereby minimizing both stray
inductance and capacitance. If leaded components are used, it is recommended that the lead lengths be kept
as short as possible.
General Power Dissipation Considerations
For a given θ
JA
, the maximum power dissipation is shown in Figure 53 and is calculated by Equation 1:
(1)
Where:
P
D
= Maximum power dissipation of TLV246x-Q1 (watts)
T
MAX
= Absolute maximum junction temperature (150°C)
T
A
= Ambient free-air temperature (°C)
θ
JA
= θ
JC
+ θ
CA
θ
JC
= Thermal coefficient from junction to case
θ
CA
= Thermal coefficient from case to ambient air (°C/W)
Figure 53. Maximum Power Dissipation vs Free-Air Temperature
Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-
Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1