Datasheet

+
V
+
I
R
R
G
S
R
I
F
IB
V
O
I
IB+
(1 ( )) (1 ( ))
F F
OO IO IB S IB F
G G
R R
V V I R I R
R R
-= + ± + + ±
C
LOAD
R
Input
F
Output
R
G
R
NULL
_
+
TLV2460-Q1, TLV2461-Q1, TLV2462-Q1, TLV2463-Q1, TLV2464-Q1
TLV2460A-Q1, TLV2461A-Q1, TLV2462A-Q1, TLV2463A-Q1, TLV2464A-Q1
www.ti.com SGLS008E –MARCH 2003–REVISED OCTOBER 2012
APPLICATION INFORMATION
Driving a Capacitive Load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the phase
margin of the device leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater
than 10 pF, it is recommended that a resistor be placed in series (R
NULL
) with the output of the amplifier, as
shown in Figure 49. A minimum value of 20 Ω works well for most applications.
Figure 49. Driving a Capacitive Load
Offset Voltage
The output offset voltage (V
OO
) is the sum of the input offset voltage (V
IO
) and both input bias currents (I
IB
) times
the corresponding gains. The schematic and formula in Figure 50 can be used to calculate the output offset
voltage.
Figure 50. Output Offset Voltage Model
Copyright © 2003–2012, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Links: TLV2460-Q1 TLV2461-Q1 TLV2462-Q1 TLV2463-Q1 TLV2464-Q1 TLV2460A-Q1 TLV2461A-
Q1 TLV2462A-Q1 TLV2463A-Q1 TLV2464A-Q1