Datasheet

TLV2401, TLV2402, TLV2404
FAMILY OF 880-nA/Ch RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS WITH REVERSE BATTERY PROTECTION
SLOS244B – FEBRUARY 2000 – REVISED NOVEMBER 2000
13
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
reverse battery protection
The TLV2401/2/4 are protected against reverse battery voltage up to 18 V. When subjected to reverse battery
condition the supply current is typically less than 100 nA at 25°C (inputs grounded and outputs open). This
current is determined by the leakage of 6 Schottky diodes and will therefore increase as the ambient
temperature increases.
When subjected to reverse battery conditions and negative voltages applied to the inputs or outputs, the input
ESD structure will turn on—this current should be limited to less than 10 mA. If the inputs or outputs are referred
to ground, rather than midrail, no extra precautions need be taken.
common-mode input range
The TLV2401/2/4 has rail-to-rail input and outputs. For common-mode inputs from –0.1 V to V
CC
– 0.8 V a PNP
differential pair will provide the gain.
For inputs between V
CC
– 0.8 V and V
CC
, two NPN emitter followers buffering a second PNP differential pair
provide the gain. This special combination of NPN/PNP differential pair enables the inputs to be taken 5 V above
the rails, because as the inputs go above V
CC
, the NPNs switch from functioning as transistors to functioning
as diodes. This will lead to an increase in input bias current. The second PNP differential pair continues to
function normally as the inputs exceed V
CC
.
The TLV2401/2/4 has a negative common-input range that exceeds ground by 100 mV. If the inputs are taken
much below this, reduced open loop gain will be observed with the ultimate possibility of phase inversion.
offset voltage
The output offset voltage, (V
OO
) is the sum of the input offset voltage (V
IO
) and both input bias currents (I
IB
) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
V
OO
V
IO
1
R
F
R
G
I
IB
R
S
1
R
F
R
G
I
IB–
R
F
+
–
V
I
+
R
G
R
S
R
F
I
IB–
V
O
I
IB+
Figure 37. Output Offset Voltage Model