Datasheet

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SLOS270D − MARCH 2001 − REVISED JANUARY 2005
14
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• DALLAS, TEXAS 75265
APPLICATION INFORMATION
rail-to-rail input operation
The TLV237x input stage consists of two differential transistor pairs, NMOS and PMOS, that operate together
to achieve rail-to-rail input operation. The transition point between these two pairs can be seen in Figure 1,
Figure 2, and Figure 3 for a 2.7-V, 5-V, and 15-V supply. As the common-mode input voltage approaches the
positive supply rail, the input pair switches from the PMOS differential pair to the NMOS differential pair. This
transition occurs approximately 1.35 V from the positive rail and results in a change in offset voltage due to
different device characteristics between the NMOS and PMOS pairs. If the input signal to the device is large
enough to swing between both rails, this transition results in a reduction in common-mode rejection ratio
(CMRR). If the input signal does not swing between both rails, it is best to bias the signal in the region where
only one input pair is active. This is the region in Figure 1 through Figure 3 where the offset voltage varies slightly
across the input range and optimal CMRR can be achieved. This has the greatest impact when operating from
a 2.7-V supply voltage.
driving a capacitive load
When the amplifier is configured in this manner, capacitive loading directly on the output decreases the device’s
phase margin leading to high frequency ringing or oscillations. Therefore, for capacitive loads of greater than
10 pF, it is recommended that a resistor be placed in series (R
NULL
) with the output of the amplifier, as shown
in Figure 33. A minimum value of 20 Ω should work well for most applications.
C
LOAD
R
F
Input
Output
R
G
R
NULL
+
−
V
DD
/2
Figure 33. Driving a Capacitive Load
offset voltage
The output offset voltage, (V
OO
) is the sum of the input offset voltage (V
IO
) and both input bias currents (I
IB
) times
the corresponding gains. The following schematic and formula can be used to calculate the output offset
voltage:
V
OO
+ V
IO
ǒ
1 ) ǒ
R
F
R
G
Ǔ
Ǔ
" I
IB)
R
S
ǒ
1 ) ǒ
R
F
R
G
Ǔ
Ǔ
" I
IB–
R
F
+
−
V
I
+
R
G
R
S
R
F
I
IB−
V
O
I
IB+
Figure 34. Output Offset Voltage Model