Datasheet
SLOS186C − FEBRUARY 1997 − REVISED AUGUST 2006
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
TLV2262 AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
V
IO
max
AT 25°C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(JG)
PLASTIC
DIP
(P)
TSSOP
(PW)
CERAMIC
FLATPACK
(U)
0°C to 70°C 2.5 mV TLV2262CD — — TLV2262CP TLV2262CPWLE —
−40°C to 125°C
950 µV
TLV2262AID
—
—
TLV2262AIP
TLV2262AIPWLE
—
−40°C to 125°C
950 µV
2.5 mV
TLV2262AID
TLV2262ID
—
—
—
—
TLV2262AIP
TLV2262IP
TLV2262AIPWLE
—
—
—
−40°C to 125°C
950 µV
TLV2262AQD
—
—
—
—
—
−40°C to 125°C
950 µV
2.5 mV
TLV2262AQD
TLV2262QD
—
—
—
—
—
—
—
—
—
—
−55°C to 125°C
950 µV
2.5 mV
—
—
TLV2262AMFK
TLV2262MFK
TLV2262AMJG
TLV2262MJG
—
—
—
—
TLV2262AMU
TLV2262MU
†
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2262CDR).
‡
The PW package is available only left-end taped and reeled.
§
Chips are tested at 25°C.
¶
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.
TLV2264 AVAILABLE OPTIONS
PACKAGED DEVICES
T
A
V
IO
max
AT 25°C
SMALL
OUTLINE
(D)
CHIP
CARRIER
(FK)
CERAMIC
DIP
(J)
PLASTIC
DIP
(N)
TSSOP
(PW)
CERAMIC
FLATPACK
(W)
−40
°
C to
950 µV
TLV2264AID
—
—
TLV2264AIN
TLV2264AIPWLE
—
−40 C to
125°C
950 µV
2.5 mV
TLV2264AID
TLV2264ID
—
—
—
—
TLV2264AIN
TLV2264IN
TLV2264AIPWLE
—
—
—
−40
°
C to
950 µV
TLV2264AQD
—
—
—
—
—
−40 C to
125°C
950 µV
2.5 mV
TLV2264AQD
TLV2264QD
—
—
—
—
—
—
—
—
—
—
−55°C to
125°C
950 µV
2.5 mV
—
—
TLV2264AMFK
TLV2264MFK
TLV2264AMJ
TLV2264MJ
—
—
—
—
TLV2264AMW
TLV2264MW
†
The D packages are available taped and reeled. Add R suffix to device type (e.g., TLV2262IDR).
‡
The PW package is available only left-end taped and reeled.
§
Chips are tested at 25°C.
¶
For the most current package and ordering information see the Package Option Addendum at the end of this document, or see the TI web site
at www.ti.com.