Datasheet
TLV2241, TLV2242, TLV2244
FAMILY OF 1-µA/Ch RAIL-TO-RAIL INPUT/OUTPUT
OPERATIONAL AMPLIFIERS
SLOS329C – JULY 2000 REVISED - NOVEMBER 2000
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
macromodel information
Macromodel information provided was derived using Microsim
Parts
Release 8, the model generation
software used with Microsim
PSpice
. The Boyle macromodel (see Note 2) and subcircuit in Figure 40 are
generated using the TLV224x typical electrical and operating characteristics at T
A
= 25°C. Using this
information, output simulations of the following key parameters can be generated to a tolerance of 20% (in most
cases):
Maximum positive output voltage swing
Maximum negative output voltage swing
Slew rate
Quiescent power dissipation
Input bias current
Open-loop voltage amplification
Unity-gain frequency
Common-mode rejection ratio
Phase margin
DC output resistance
AC output resistance
Short-circuit output current limit
NOTE 2: G. R. Boyle, B. M. Cohn, D. O. Pederson, and J. E. Solomon, “Macromodeling of Integrated Circuit Operational Amplifiers”,
IEEE Journal
of Solid-State Circuits,
SC-9, 353 (1974).
.subckt 224X_5V–X 1 2 3 4 5
*
c1 11 12 9.8944E–12
c2 6 7 30.000E–12
cee 10 99 8.8738E–12
dc 5 53 dy
de 54 5 dy
dlp 90 91 dx
dln 92 90 dx
dp 43dx
egnd 99 0 poly(2) (3,0) (4,0) 0 .5 .5
fb 7 99 poly(5) vb vc ve vlp vln 0 61.404E6 –1E3 1E3 61E6 –61E6
ga 6 0 11 12 1.0216E–6
gcm 0 6 10 99 10.216E–12
iee 10 4 dc 54.540E–9
ioff 0 6 dc 5e–12
hlim 90 0 vlim 1K
q1 11 2 13 qx1
q2 12 1 14 qx2
r2 6 9 100.00E3
rc1 3 11 978.81E3
rc2 3 12 978.81E3
re1 13 10 30.364E3
re2 14 10 30.364E3
ree 10 99 3.6670E9
ro1 8 5 10
ro2 7 99 10
rp 3 4 1.4183E6
vb 9 0 dc 0
vc 3 53 dc .88315
ve 54 4 dc .88315
vlim 7 8 dc 0
vlp 91 0 dc 540
vln 0 92 dc 540
.model dx D(Is=800.00E–18)
.model dy D(Is=800.00E–18 Rs=1m Cjo=10p)
.model qx1 NPN(Is=800.00E–18 Bf=27.270E21)
.model qx2 NPN(Is=800.0000E–18 Bf=27.270E21)
.ends
13
rp
IN+
rc1 rc2
ree
egnd
fb
ro2
ro1
vlim
V
OUT
ga
ioffgcm
vb
c1
dc
iee
re2re1
dp
V
CC–
V
CC+
IN–
q1 q2
cee
c2
ve
de
dlp dln
vlnhlimvlp
14
10
4
2
1
11 12
3
53
54
96
8
5
7
91 90 92
vc
99
+
+
+
+
+
+
+
–
–
–
–
––
–
–
+
r2
Figure 40. Boyle Macromodels and Subcircuit
PSpice
and
Parts
are trademarks of MicroSim Corporation.