Datasheet
SLOS157B − JUNE 1996 − REVISED APRIL 2005
25
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APPLICATION INFORMATION
driving large capacitive loads
The TLV2221 is designed to drive larger capacitive loads than most CMOS operational amplifiers. Figure 50
through Figure 55 illustrate its ability to drive loads greater than 100 pF while maintaining good gain and phase
margins (R
null
= 0).
A small series resistor (R
null
) at the output of the device (Figure 56) improves the gain and phase margins when
driving large capacitive loads. Figure 50 through Figure 53 show the effects of adding series resistances of
100 Ω, 200 Ω, 500 Ω, and 1 kΩ. The addition of this series resistor has two effects: the first effect is that it adds
a zero to the transfer function and the second effect is that it reduces the frequency of the pole associated with
the output load in the transfer function.
The zero introduced to the transfer function is equal to the series resistance times the load capacitance. To
calculate the approximate improvement in phase margin, equation 1 can be used.
∆φ
m1
+ tan
–1
ǒ
2 ×π×UGBW × R
null
× C
L
Ǔ
∆φ
m1
+ improvement in phase margin
UGBW + unity-gain bandwidth frequency
R
null
+ output series resistance
C
L
+ load capacitance
(1)
where :
The unity-gain bandwidth (UGBW) frequency decreases as the capacitive load increases (Figure 54 and Figure
55). To use equation 1, UGBW must be approximated from Figure 54 and Figure 55.
V
DD−
/GND
V
DD+
R
null
C
L
V
I
+
−
R
L
Figure 56. Series-Resistance Circuit
The TLV2221 is designed to provide better sinking and sourcing output currents than earlier CMOS rail-to-rail
output devices. This device is specified to sink 500 µA and source 1 mA at V
DD
= 5 V at a maximum quiescent
I
DD
of 200 µA. This provides a greater than 80% power efficiency.
When driving heavy dc loads, such as 2 kΩ, the positive edge under slewing conditions can experience some
distortion. This condition can be seen in Figure 38. This condition is affected by three factors:
D Where the load is referenced. When the load is referenced to either rail, this condition does not occur. The
distortion occurs only when the output signal swings through the point where the load is referenced.
Figure 39 illustrates two 2-kΩ load conditions. The first load condition shows the distortion seen for a 2-kΩ
load tied to 2.5 V. The third load condition in Figure 39 shows no distortion for a 2-kΩ load tied to 0 V.
D Load resistance. As the load resistance increases, the distortion seen on the output decreases. Figure 39
illustrates the difference seen on the output for a 2-kΩ load and a 100-kΩ load with both tied to 2.5 V.
D Input signal edge rate. Faster input edge rates for a step input result in more distortion than with slower input
edge rates.