Datasheet

TLV1572
2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTO-POWERDOWN
SLAS171A – DECEMBER 1997– REVISED SEPTEMBER 1998
9
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
interfacing TLV1572 to TMS320 DSPs (continued)
The TLV1572 goes into auto-powerdown after the LSB is shifted out. The next FS pulls it out of auto-powerdown
as shown in Figure 5. If FS comes on the 16th bit, the next conversion cycle starts from the next rising edge
of SCLK allowing back to back conversions as shown in Figure 6. An FS high in the middle of a conversion cycle
resets the device and starts a new conversion cycle. Therefore variable-bit transfer is supported if FS appears
earlier.
CS
can be pulled high asynchronously to put the device into 3-state and powerdown. CS can also be pulled low
asynchronously to start checking for FS on the falling edges of the clock.
1234567 16
0
0 0
0
0
0
LSB(N)
SCLK
CS
FS
DO
MSB
1234567 16
0 0
0
0 0
0
LSB(N+1)
MSB(N+1)
Autopower Down
Sampling Conversion
Sample (N) Sample (N+1)
(N)
6 Leading Zeros
Figure 5. DSP Application Timing (Intermittent Conversion)
1234567 16
0
0 0
0
0 0
SCLK
CS
FS
DO
MSB
1234567 16
0 0 0 0 0
0
0
LSB(N)
LSB(N+1)
Sampling Conversion
Sample (N) Sample (N+1)
(N)
6 Leading
Zeros
MSB(N+1)
Figure 6. DSP Application Timing (Continuous Conversion)
key points
1. When CS
goes low, if FS is low, it is in DSP mode. FS is sampled twice by a CS falling edge and again by
an internally delayed CS
falling edge. Even if a glitch appears and one latch latches 1 and another latches
0, the device goes into DSP mode (µC mode requires both latches to latch 1). There is a hold time before
FS can go high again after the CS
falling edge to ensure proper mode latching as detailed above. With CS
going low, DO is in 3-state and the device is in powerdown until a FS rising edge.
2. The TLV1572 checks for FS at every falling edge of SCLK. If FS is detected high, the device goes into reset.
When FS goes low, the TLV1572 waits for the DSP to latch the first 0 bit.
3. Sampling occurs from first falling edge of SCLK after FS going low until the rising edge when the 6th 0 bit
is sent out. Thereafter decisions are taken on the rising edges and data is sent out on the rising edges (1
bit delayed). The DSP samples on the falling edge of SCLK. Data is padded with 6 leading zeros.