Datasheet

TLV1572
2.7 V TO 5.5 V, 10-BIT, 1.25 MSPS
SERIAL ANALOG-TO-DIGITAL CONVERTER WITH AUTO-POWERDOWN
SLAS171A – DECEMBER 1997– REVISED SEPTEMBER 1998
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATION INFORMATION
key points (continued)123
4. Note that the device goes into autopower down on the 17th falling edge of SCLK (just after the LSB). The
FS rising edge pulls it out of autopower down. If FS comes on the 16th bit, the next conversion cycle starts
from the next rising edge allowing back to back conversions. An FS in the middle of a conversion cycle starts
a new conversion cycle. Thus variable-bit transfer is supported if FS appears earlier.
5. DO goes into 3-state on the 17th rising edge and comes out on a FS rising edge.
6. CS
can be pulled high asynchronously to put the device into 3-state and powerdown. CS may also be pulled
low asynchronously to start checking for FS on the falling edges of the clock.
For applications where the analog input must be sampled at a precise instant in time, data conversion can be
initiated by an external conversion start pulse which is completely asynchronous to the SCLK as shown in Figure
4. When a conversion start pulse is received, the pulse is used as a frame sync (FS) signal to initiate the data
conversion and transfer. The corresponding timing diagram is shown in Figure 6.
interfacing TLV1572 to SPI/QSPI compatible microcontrollers (µCs)
The TLV1572 is compatible with SPI and QSPI serial interface standards (Note: the TLV1572 supports the
following SPI clock options: clock_polarity= 0, i.e. SCLK idles low, and clock_phase = 1). Figure 7 shows the
pin connections to interface the TLV1572 to SPI/QSPI compatible microcontrollers.
CS
SCLK
FS
DO
XF
SCLK
DR
TLV1572 µC
V
CC
Figure 7. TLV1572 to µC Interface
1 2 345 67 16
0 0 0
0
0
0 MSB
SCLK
CS
FS
SDOUT
LSB
Figure 8. Typical Timing Diagram for µC Application
To use the TLV1572 in a non-DSP application, the FS input must be pulled high as shown in Figure 8.
A total of 16 clocks are normally supplied for each conversion. If the µC cannot take in 16 bits at a time, it may
take 8 bits with 8 clocks and next 8 bits with another 8 clocks. CS must be kept low throughout the conversion.
The delay between these two 8-clock periods must not be longer than 100 µs.