Datasheet

TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
6
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
DSP interface
The TLV1544/1548 can also interface with a DSP, from the TMS320 family for example, through a serial port.
The analog-to-digital converter (ADC) serves as a slave device where the DSP supplies FS and the serial I/O
CLK. Transmit and receive operations are concurrent. The falling edge of FS must occur no later than seven
I/O CLK periods after the falling edge of CS
.
DSP I/O cycles differ from microprocessor I/O cycles in the following ways:
When interfaced with a DSP, the output data MSB is available after FS↓. The remaining output data changes
on the rising edge of I/O CLK. The input data is sampled on the first four falling edges of I/O CLK after FS↓
and when INV CLK
is high, or the first four rising edges of I/O CLK after FS↓ and when INV CLK is low. This
operation is inverted when interfaced with a microprocessor.
A new DSP I/O cycle is started on the rising edge of I/O CLK after the rising edge of FS. The internal state
machine is reset on each falling edge of I/O CLK when FS is high. This operation is opposite when interfaced
with a microprocessor.
The TLV1544/1548 supports a 16-clock cycle when interfaced with a DSP. The output data is padded with
six trailing zeros when it is operated in DSP mode.
Table 2. TLV1544/TLV1548 Serial Interface Modes
I/O
INTERFACE MODE
I/O
MICROPROCESSOR ACTION DSP ACTION
CS↓ Initializes counter Samples state of FS
CS↑ Resets state machine and disable I/O Disables I/O
FS Connects to V
CC
Connects to DSP FSX output
Initializes the state machine at each CLK↓ after FS↑
Starts a new cycle at each CLK↑ following the initialization
(initializes the counter)
I/O CLK
Starts sampling of the analog input started at fourth I/O CLK↑
Conversion started at tenth I/O CLK↑
Starts sampling of the analog input at fourth I/O CLK↓
Starts sampling of the analog input at tenth I/O CLK↓
DATA IN
Samples input data on I/O CLK↑ (INV CLK high)
Samples input data on I/O CLK↓ (INV CLK
low)
Samples input data at I/O CLK↓ (INV CLK high)
Samples input data at I/O CLK↑ (INV CLK
low)
DATA OUT
Makes MSB available on CS↓
Changes remaining data on I/O CLK↓
Makes MSB available FS↓
Changes remaining data at each following I/O CLK↑ after
FS↓