Datasheet

TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
31
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
APPLICATIONS INFORMATION
R
s
r
i
V
S
V
C
55 pF MAX
1 kΩ
Driving Source
†
TLV1544/48
C
i
V
I
V
I
= Input Voltage at AIN
V
S
= External Driving Source Voltage
R
s
= Source Resistance
r
i
= Input Resistance (MUX on Resistance)
C
i
= Input Capacitance
V
C
= Capacitance Charging Voltage
†
Driving source requirements:
• Noise and distortion for the source must be equivalent to the resolution of the converter.
• R
s
must be real at the input frequency.
Figure 40. Equivalent Input Circuit Including the Driving Source
maximum conversion throughput
For a supply voltage at 5 V,
if the source impedance is less than 1 kΩ, this equates to a minimum sampling
time t
ch
(0.5 LSB) of 0.84 µs. Since the sampling time requires six I/O clocks, the fastest I/O clockfrequency is
6/t
ch
= 7.18 MHz. The minimal total cycle time is given as:
t
c
= t
address
+ t
sample
+ t
conv
+ t
d(EOC↑ – CS↓)
= 0.56 µs + 0.84 µs + 10 µs + 0.1 µs
= 11.5 µs
A maximum throughput of 87 KSPS. The throughput can be even higher with a smaller source impedance.
When source impedance is 100Ω, the minimum sampling time is 0.46 µs. The maximum I/O clock frequency
possible is almost 13 MHz. Then 10 MHz clock (maximum I/O CLK for TLV1544/1548) can be used. The minimal
total cycle time is:
t
c
= t
address
+ t
sample
+ t
conv
+ t
d(EOC↑ – CS↓)
= 4 × 1/f + 0.46 µs + 10 µs + 0.1 µs
= 0.4 µs + 0.46 µs + 10 µs + 0.1 µs
= 10.96 µs
The maximum throughput is 1/10.96 µs = 91 KSPS for this case.