Datasheet

TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
20
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PARAMETER MEASUREMENT INFORMATION
t
d(EOC↑-CS↓)
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input
signals. No attempt should be made to clock in input data until the minimum CS
setup time elapses.
1 2 3 4 5 6 7 8 9 10
I/O CLK
Conversion
Sample
(6 I/O CLKs)
DI
DO
EOC
CS
MSB
MSB LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-ZHi-Z
A3 A2 A1 A0
Rise After 10th I/O CLK↓
(see Note A)
Address Sampled
Initialize State Machine
and Counter
Access
Conversion Starts on 10th I/O CLK↑
0s
A
3
D
9
Figure 16. Microprocessor Interface Timing (Normal Sample Mode, INV CLK = High)
NOTE A: To minimize errors caused by noise at CS, the internal circuitry waits for a setup time after CS↓ before responding to control input
signals. No attempt should be made to clock in input data until the minimum CS
setup time has elapsed.
t
d(EOC↑-CS↓)
1 2 3 45678910
I/O CLK
Conversion
Sample
DI
DO
EOC
CS
MSB
MSB LSB
D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Hi-ZHi-Z
A2 A1 A0
Rise After 10th I/O CLK↓
(see Note A)
Address Sampled
Conversion Starts on 10th I/O CLK↑
Initialize State Machine
and Counter
(5.5 I/O CLKs)
Access
0s
A
3
D
9
A3
Figure 17. Microprocessor Interface Timing (Normal Sample Mode, INV CLK = Low)