Datasheet

TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
16
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
operating characteristics over recommended operating free-air temperature range,
V
CC
= V
ref+
= 2.7 V to 5.5 V, I/O CLK frequency = 2.2 MHz (unless otherwise noted)
PARAMETER
TEST
CONDITIONS
MIN TYP
†
MAX UNIT
E
L
Linearity error (see Note 6) ±0.5 ±1 LSB
E
D
Differential linearity error See Note 2 ±0.5 ±1 LSB
E
O
Offset error (see Note 7) See Note 2 ±1.5 LSB
E
G
Gain error (see Note 7) See Note 2 ±1 LSB
E
T
Total unadjusted error (see Note 8) ±1.75 LSB
DATA IN = 1011 512
Self-test output code (see Table 3 and Note 9)
DATA IN - 1100 0
DATA IN = 1101 1023
t
Conversion time
Fast conversion speed
See Figures 15
7 10 µs
t
conv
Con
v
ersion
time
Slow conversion speed
g
through 17
15 25 µs
t
Total cycle time (access,
sam
p
le conversion and EOC↑
Fast conversion speed
See Figures 15
through 18 and
Notes 10, 11, 12
10.1 +
10 I/O CLK
µs
t
c
samp
l
e, convers
i
on an
d
EOC↑
to CS↓ delay)
Slow conversion speed
See Figures 15
through 18 and
Notes 10 and 12
40.1 +
10 I/O CLK
µ
s
t
acq
Channel acquisition time (sample)
See Figures 15
through 18 and
Note 10
6
I/O CLK
periods
t
v
Valid time, DATA OUT remains valid after I/O CLK↓ See Figure 11 50 ns
t
d1(FS)
Delay time, I/O CLK high to FS high See Figure 13 5 30 50 ns
t
d2(FS)
Delay time, I/O CLK high to FS low See Figure 13 10 30 60 ns
t
d(EOC↑ – CS↓)
Delay time, EOC↑ to CS low
See Figure 14
and Note 5
100 ns
t
d(CS↓ – FS↑)
Delay time, CS↓ to FS↑
See Figures 17
and 18
1 7
I/O CLK
periods
t
d(I/O -CS)
Delay time, 10th I/O CLK low to CS low to abort
conversion (see Note 13)
See Figure 10 1.1 µs
†
All typical values are at T
A
= 25°C.
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (111111111111), while input voltages less than that
applied to REF– convert as all zeros (000000000000). The device is functional with reference down to 1 V (V
ref
+ – V
ref
– 1); however,
the electrical specifications are no longer applicable.
5. For all operating modes.
6. Linearity error is the maximum deviation from the best straight line through the A/D transfer characteristics.
7. Zero error is the difference between 0000000000 and the converted output for zero input voltage. Full-scale error is the difference
between 1111111111 and the converted output for full-scale input voltage.
8. Total unadjusted error comprises linearity, zero-scale, and full-scale errors.
9. Both the input data and the output codes are expressed in positive logic.
10. I/O CLK period = 1/(I/O CLK frequency) (see Figure 8).
11. For 3.3 V to 5.5 V only
12. For microprocessor mode
13. Any transitions of CS
are recognized as valid only when the level is maintained for a setup time after the transition.