Datasheet

TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
14
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
2.7 5.5 V
Positive reference voltage, V
ref+
(see Note 2) V
CC
V
Negative reference voltage, V
ref–
(see Note 2) 0 V
Differential reference voltage, V
ref+
– V
ref–
(see Note 2) 2.5 V
CC
V
CC
+0.2 V
Analog input voltage, V
I (analog)
(see Note 2) 0 V
CC
V
High-level control input voltage, V
IH
2.1 V
Low-level control input voltage, V
IL
0.6 V
Setup time, input data bits valid before I/O CLK↑↓, t
su(A)
(see Figure 9) 100 ns
Hold time, input data bits valid after I/O CLK↑↓, t
h(A)
(see Figure 9) 5 30 ns
Setup time, CS↓ to I/O CLK↑, t
su(CS)
See Figure 10 5 30 ns
Hold time, I/O CLK↓ to CS↑, t
h(CS)
See Figure 10 65 ns
Pulse duration, FS high, t
wH(FS)
See Figure 12 1
I/O CLK
periods
Pulse duration, CSTART, t
w(CSTART)
Source impedance ≤ 1 kΩ, V
CC
= 5.5 V,
See Figure 14
0.84 µs
Setup time, CS↑ to CSTART↓, t
su(CSTART)
See Figure 14 10 ns
Clock frequency at I/O CLK f
CLK
V
CC
= 5.5 V 0.1 6 10
MHz
Clock
freq
u
enc
y
at
I/O
CLK
,
f
CLK
V
CC
= 2.7 V 0.1 2 2.81
MH
z
Pulse duration I/O CLK high t
H(I/O)
V
CC
= 5.5 V 50
ns
P
u
lse
d
u
ration
,
I/O
CLK
high
,
t
wH(I/O)
V
CC
= 2.7 V 100
ns
Pulse duration I/O CLK low t
L(I/O)
V
CC
= 5.5 V 50
ns
P
u
lse
d
u
ration
,
I/O
CLK
lo
w,
t
wL(I/O)
V
CC
= 2.7 V 100
ns
Transition time, I/O CLK, t
t(I/O)
(see Figure 11 and Note 4) 1 µs
Transition time, DATA IN, t
t(DATA IN)
(see Figure 9) 10 µs
Transition time, CS, t
t(CS)
(see Figure 10) 10 µs
Transition time, FS, t
t(FS)
(see Figure 13) 10 µs
Transition time, CSTART, t
t(CSTART)
(see Figure 14) 10 µs
TLV1544C, TLV1548C 0 70
Operating free-air temperature, T
A
TLV1544I, TLV1548I –40 85
°C
TLV1548M –55 125
TLV1544C, TLV1548C 115
Junction temperature, T
J
TLV1544I, TLV1548I 115
°C
TLV1548M 150
NOTES: 2. Analog input voltages greater than the voltage applied to REF+ convert as all ones (111111111111), while input voltages less than
the voltage applied to REF– convert as all zeros (000000000000). The device is functional with reference (V
ref+
– V
ref–
) down to 1
V; however, the electrical specifications are no longer applicable.
3. To minimize errors caused by noise at CS
↓, the internal circuitry waits for a setup time after CS↓ before responding to control input
signals. No attempt should be made to clock in an input dat until the minimum CS
setup time has elapsed.
4. This is the time required for the I/O CLK signal to fall from V
IH
max to V
IL
min or to rise from V
IL
max to V
IH
min. In the vicinity of normal
room temperature, the devices function with an input clock transition time as slow as 1 µs for remote data-acquisition applications
where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.