Datasheet

TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M
LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS
WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS
SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
9h 0h Ab
X
D0
MUX Address for Channel 0
AsyncFlag Reset LowConversion Rate Set to Fast
Conversion Result From Channel 0
CS
DATA IN
DATA OUT
EOC
Signal Channel 0 Converted
FS
(For DSP Mode)
First Cycle After Powerup
Async Flag
(Internal)
Hi–Z Hi–Z Hi–Z Hi–Z
X
Figure 4. Power Up Initialization
input clock inversion – INV CLK
The input data register uses I/O CLK as the source of the sampling clock. This clock can be inverted to provide
more setup time. INV CLK
can invert the clock. When INV CLK is grounded, the input clock for the input data
register is inverted. This allows an additional one-half I/O CLK period for the input data setup time. This is useful
for some serial interfaces. When the input sampling clock is inverted, the output data changes at the same time
that the input data is sampled.
Table 6. Function of INV CLK
CONDITION
CLOCK
I/O CLK ACTIVE EDGE
INV CLK FS at CS↓
OUTPUT DATA
CHANGES ON
INPUT DATA
SAMPLED ON
High High (MP
†
mode) ↓ ↑
High Low (DSP
‡
mode) ↑ ↓
Low High (MP
†
mode) ↓ ↓
Low Low (DSP
‡
mode) ↑ ↑
†
MP = microprocessor mode
‡
DSP = digital signal processor mode