Datasheet

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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M

LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS

WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS

SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999

POST OFFICE BOX 655303 • DALLAS, TEXAS 75265

Conversion Time ≤ 10 µs

10-Bit-Resolution ADC

Programmable Power-Down

Mode ...1 µA

Wide Range Single-Supply Operation of

2.7 V dc to 5.5 V dc

Analog Input Range of 0 V to V

Built-in Analog Multiplexer with 8 Analog

Input Channels

TMS320 DSP and Microprocessor SPI and

QSPI Compatible Serial Interfaces

End-of-Conversion (EOC) Flag

Inherent Sample-and-Hold Function

Built-In Self-Test Modes

Programmable Power and Conversion Rate

Asynchronous Start of Conversion for

Extended Sampling

Hardware I/O Clock Phase Adjust Input

description

The TLV1544 and TLV1548 are CMOS 10-bit

switched-capacitor successive-approximation (SAR)

analog-to-digital (A/D) converters. Each device

has a chip select (CS

), input-output clock (I/O

CLK), data input (DATA IN) and serial data output

(DATA OUT) that provide a direct 4-wire

synchronous serial peripheral interface (SPI,

QSPI) port of a host microprocessor. When

interfacing with a TMS320 DSP, an additional

frame sync signal (FS) indicates the start of a

serial data frame. The devices allow high-speed

data transfers from the host. The INV CLK

input

provides further timing flexibility for the serial

interface.

In addition to a high-speed converter and versatile

control capability, the device has an on-chip

11-channel multiplexer that can select any one of

eight analog inputs or any one of three internal self-test voltages. The sample-and-hold function is automatic

except for the extended sampling cycle, where the sampling cycle is started by the falling edge of asynchronous

CSTART

. At the end of the A/D conversion, the end-of-conversion (EOC) output goes high to indicate that the

conversion is complete. The TLV1544 and TLV1548 are designed to operate with a wide range of supply

voltages with very low power consumption. The power saving feature is further enhanced with a

software-programmed power-down mode and conversion rate. The converter incorporated in the device

features differential high-impedance reference inputs that facilitate ratiometric conversion, scaling, and

isolation of analog circuitry from logic and supply noise. A switched-capacitor design allows low-error

conversion over the full operating temperature range.

SPI and QSPI are registered trademarks of Motorola, Inc.

CSTART

GND

EOC

I/O CLK

DATA IN

DATA OUT

REF+

REF–

INV CLK

DB OR J PACKAGE

(TOP VIEW)

DATA OUT

DATA IN

I/O CLK

EOC

REF+

REF–

INV CLK

GND

CSTART

D OR PW PACKAGE

(TOP VIEW)

1920132

1312119 10

I/O CLK

DATA IN

DATA OUT

REF+

EOC

GND

INV CLK

REF–

CSTART

FK PACKAGE

(TOP VIEW)

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Summary of content (38 pages)

PAGE 1
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 VCC EOC I/O CLK DATA IN DATA OUT CS REF+ REF– FS INV CLK EOC FK PACKAGE (TOP VIEW) VCC 3 2 1 20 19 A3 4 18 I/O CLK A4 5 17 DATA IN A5 6 16 DATA OUT A6 7 15 CS A7 8 14 REF+ 9 10 11 12 13 REF– The TLV1544 and TLV1548 are CMOS 10-bit switched-capacitor successive-approximation (SAR) analog-to-digital
PAGE 2
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 description (continued) The TLV1544 has four analog input channels while the TLV1548 has eight analog input channels. The TLV1544C and TLV1548C are characterized for operation from 0°C to 70°C. The TLV1544I and TLV1548I are characterized for operation over the full industrial temperature range of –40°C to 85°C.
PAGE 3
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 Terminal Functions TERMINAL NO.† NAME NO.‡ I/O DESCRIPTION A0–A3 A4–A7 6–9 – 1–4 5–8 I Analog inputs. The analog inputs are internally multiplexed. (For a source impedance greater than 1 kΩ, the asynchronous start should be used to increase the sampling time.) CS 16 15 I Chip select.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 Terminal Functions (Continued) TERMINAL NO.† NO.‡ NAME I/O CLK 3 I/O DESCRIPTION I Input/output clock.
PAGE 5
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 I/O CLK The I/O CLK can go up to 10 MHz for most of the voltage range when fast I/O is possible. The maximum I/O CLK is limited to 2.8 MHz for a supply voltage range from 2.7 V. Table 1 lists the maximum I/O CLK frequencies for all different supply voltage ranges. This also depends on input source impedance.
PAGE 6
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 DSP interface The TLV1544/1548 can also interface with a DSP, from the TMS320 family for example, through a serial port. The analog-to-digital converter (ADC) serves as a slave device where the DSP supplies FS and the serial I/O CLK. Transmit and receive operations are concurrent.
PAGE 7
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 input data bits DATA IN is internally connected to a 4-bit serial input data register. The input data selects a different mode or selects different analog input channels. The host provides the data word with the MSB first.
PAGE 8
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 converter The CMOS threshold detector in the successive-approximation conversion system determines the value of each bit by examining the charge on a series of binary-weighted capacitors (see Figure 1).
PAGE 9
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 extended sampling, asynchronous start of sampling: CSTART operation The extended sampling mode of operation programs the acquisition time (tACQ) of the sample-and-hold circuit. This allows the analog inputs of the device to be directly interfaced to a wide range of input source impedances.
PAGE 10
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 Complete Extended Sample Cycle Extended Sample Cycle Normal Cycle Extended Sample Cycle Read Out Cycle Read Out Cycle Read Out Cycle Normal Cycle CS FS (DSP Mode) tACQ tACQ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎ CSTART DATA IN Aa Ab Ab Ac Ad EOC D
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 Table 5. Conversion Rate and Power Consumption Selection TYPICAL SUPPLY CURRENT, ICC CONVERSION TIME TIME, tconv AVAILABLE VCC RANGE Fast conversion speed 7 µs typ 5.5 V to 3.3 V 9h 0.6 mA typ 1.5 mA max 1 µA typ Slow conversion speed 15 µs typ 5.5 V to 2.7 V Ah 0.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 First Cycle After Powerup MUX Address for Channel 0 CS FS (For DSP Mode) Async Flag (Internal) DATA IN ÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ 9h 0h Ab Signal Channel 0 Converted EOC DATA OUT Hi–Z Hi–Z X Conversion Rate Set to Fast Hi–Z Hi–Z D0 X Conversion Result From Channel 0 A
PAGE 13
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 Threshold Detect REF+ REF– SampleandHold Function A0–A7 11-to-1 Analog MUX TEST 0–2 DATA OUT Output Shift Clock Invert Vref REF– SAR† Latch 10-to-1 Select Conversion Clock REF+ EOC INV CLK If_mode DATA IN If_mode OSC Input Data Register SMCLK Input Shift Clock 2-to-1 Invert 2-to-1 DSP§ If_mode CS FS I/
PAGE 14
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 recommended operating conditions MIN Supply voltage, VCC NOM 2.7 Positive reference voltage, Vref + (see Note 2) MAX 5.5 VCC 0 Negative reference voltage, Vref – (see Note 2) Differential reference voltage, Vref + – Vref – (see Note 2) 2.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 electrical characteristics over recommended operating free-air temperature range, VCC = Vref+ = 2.7 V to 5.5 V, I/O CLK frequency = 2.2 MHz (unless otherwise noted) PARAMETER TEST CONDITIONS TYP† MAX VOH High level output voltage High-level VOL Low level output voltage Low-level VCC = 5.5 V, VCC = 2.7 V, IOL = 0.
PAGE 16
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 2.7 V to 5.5 V, I/O CLK frequency = 2.2 MHz (unless otherwise noted) TEST CONDITIONS PARAMETER MIN TYP† MAX UNIT ±0.5 ±1 LSB ±0.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 operating characteristics over recommended operating free-air temperature range, VCC = Vref+ = 2.7 V to 5.5 V, I/O CLK frequency = 2.
PAGE 18
TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION Address Valid 90% CS 10% 10% 90% 10% 10% VOH 10% th(A) VIH 10% VOL tt(I/O) tt(CS) VIH 90% 10% 10% VIL th(CS) tsu(CS) td(I/O-CS) I/O CLK First Clock 10% Last Clock 10% VIL Figure 10.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION 10th Clock I/O CLK 10% 10% VIL td(I/O-EOC) VOH EOC (µp Mode) 10% VOL td(I/O-EOC) EOC (DSP Mode) VOH 90% 10% VOL tf(EOC) Figure 13.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION Address Sampled Conversion Starts on 10th I/O CLK↑ Rise After 10th I/O CLK↓ Conversion Access td(EOC↑-CS↓) Sample (6 I/O CLKs) CS (see Note A) 1 2 3 4 A3 A2 A1 A0 D8 D7 D6 5 6 7 8 9 10 I/O CLK ÎÎÎ ÎÎÎ DI MSB Hi-Z DO D9 ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ ÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎÎ A3
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION Initialize Counter Address Sampled Conversion Starts on 10th I/O CLK↓ CS Rise After 16th I/O CLK↓ td(EOC↑-CS↓) Initialize State Machine 7 I/O CLKs Maximum Access Sample (6 I/O CLKs) CS (see Note A) 1 2 3 4 5 A3 A2 A1 A0 D8 D7 D6 6 7 Hold/Conversion 8 9 10 11 12 1
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 PARAMETER MEASUREMENT INFORMATION Initialize Counter Address Sampled Conversion Starts on 10th I/O CLK↓ CS Rise After 16th I/O CLK↓ td(EOC↑-CS↓) Initialize State Machine 7 I/O CLKs Maximum Access Sample (6 I/O CLKs) CS (see Note A) 1 2 3 4 A3 A2 A1 A0 D8 D7 D6 5 6 7 8 Hold/Conversion 9 10 11 12 1
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY ERROR vs FREE-AIR TEMPERATURE 0.4 0.5 0.3 0.4 INL – Integral Nonlinearity Error – LSB INL – Integral Nonlinearity Error – LSB INTEGRAL NONLINEARITY ERROR vs FREE-AIR TEMPERATURE Maximum 0.2 0.1 VCC = 2.7 V 0 –0.1 –0.2 Minimum –0.3 –0.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 TYPICAL CHARACTERISTICS OFFSET ERROR vs FREE-AIR TEMPERATURE GAIN ERROR vs FREE-AIR TEMPERATURE 0.35 0.7 VCC = 2.7 V 0.3 EG – Gain Error – LSB 0.6 EO – Offset Error – LSB 0.25 VCC = 5.5 V 0.2 0.15 0.1 0.5 0.4 VCC = 2.7 V 0.3 0.2 VCC = 5.5 V 0.05 0 –75 0.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 TYPICAL CHARACTERISTICS SUPPLY CURRENT vs FREE-AIR TEMPERATURE 0.56 I CC – Supply Current – mA 0.54 0.52 0.5 0.48 0.46 0.44 0.42 VCC = 5.5 V Clock Mode = Fast Conversion 0.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODE DIFFERENTIAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODE 1 1 INL – Integral Nonlinearity Error – LSB 0.8 0.6 DNL – Differential Nonlinearity Error – LSB VCC = 5 V TA = –40°C Clock Mode = Fast 0.4 0.2 0 –0.2 –0.4 –0.6 –0.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 TYPICAL CHARACTERISTICS INTEGRAL NONLINEARITY ERROR vs DIGITAL OUTPUT CODE 1 VCC = 5 V TA = 85°C Clock Mode = Fast INL – Integral Nonlinearity Error – LSB 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 APPLICATION INFORMATION 1023 1111111111 VFS See Notes A and B 1022 1111111110 VFSnom 1021 VFT = VFS – 1/2 LSB 513 1000000001 512 1000000000 VZT = VZS + 1/2 LSB Step Digital Output Code 1111111101 511 0111111111 VZS 0000000001 1 0000000000 0 0.0048 0.0096 2.4528 2.4576 2.4624 4.9128 4.9080 2 0.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 APPLICATION INFORMATION VCC 20 12 11 VCC FS TLV1548† Microprocessor 15 CS INV CLK I/O CLK DX DR 14 REF+ 3 V dc Regulated 13 REF– GND CLKR 16 DATA OUT A0–A7 Analog Inputs CLKX 17 DATA IN 1–8 I/O 2 18 10 To Source Ground † DB package is shown for TLV1548 Figure 38.
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 APPLICATIONS INFORMATION simplified analog input analysis Using the equivalent circuit in Figure 33, the time required to charge the analog input capacitance from 0 to VS within 1/2 LSB can be derived as follows: ǒ Ǔ The capacitance charging voltage is given by: V C + VS 1–e–tcńRtCi where (1) Rt = Rs + ri tc = Cycl
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TLV1544C, TLV1544I, TLV1548C, TLV1548I, TLV1548M LOW-VOLTAGE 10-BIT ANALOG-TO-DIGITAL CONVERTERS WITH SERIAL CONTROL AND 4/8 ANALOG INPUTS SLAS139C – DECEMBER 1996 – REVISED JANUARY 1999 APPLICATIONS INFORMATION Driving Source† TLV1544/48 Rs VS ri VI VC 1 kΩ Ci 55 pF MAX VI = Input Voltage at AIN VS = External Driving Source Voltage Rs = Source Resistance ri = Input Resistance (MUX on Resistance) Ci = Input Capacitance VC = Capacitance Charging Voltage † Driving source requirements: • Noise and dist
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 26-Sep-2013 (2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability information and additional product content details. TBD: The Pb-Free/Green conversion plan has not been defined.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.3 2.1 8.0 16.0 Q1 TLV1544CDR SOIC D 16 2500 330.0 16.4 6.5 TLV1544CPWR TSSOP PW 16 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TLV1544IDR SOIC D 16 2500 330.0 16.4 6.5 10.3 2.1 8.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLV1544CDR SOIC D 16 2500 367.0 367.0 38.0 TLV1544CPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLV1544IDR SOIC D 16 2500 367.0 367.0 38.0 TLV1544IPWR TSSOP PW 16 2000 367.0 367.0 35.0 TLV1548CDBR SSOP DB 20 2000 367.0 367.0 38.0 TLV1548IDBR SSOP DB 20 2000 367.0 367.0 38.
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