Datasheet

  
   
      
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
8
WWW.TI.COM
recommended operating conditions
MIN NOM MAX UNIT
Supply voltage, V
CC
TLV1543C/TLV1543I 3 3.3 5.5 V
Supply voltage, V
CC
TLV1543M 3 3.3 3.6 V
Positive reference voltage, V
ref+
(see Note 2) V
CC
V
Negative reference voltage, V
ref−
(see Note 2) 0 V
Differential reference voltage, V
ref+
− V
ref−
(see Note 2) 2.5 V
CC
V
CC
+0.2 V
Analog input voltage (see Note 2) 0 V
CC
V
High-level control input voltage, V
IH
TLV1543C/TLV1543I V
CC
= 3 V to 5.5 V 2 V
High-level control input voltage, V
IH
TLV1543M V
CC
= 3 V to 3.6 V 2 V
Low-level control input voltage, V
IL
TLV1543C/TLV1543I V
CC
= 3 V to 5.5 V 0.6 V
Low-level control input voltage, V
IL
TLV1543M V
CC
= 3 V to 3.6 V 0.8 V
Setup time, address bits at data input before I/O CLOCK↑, t
su(A)
(see Figure 4) 100 ns
Hold time, address bits after I/O CLOCK↑, t
h(A)
(see Figure 4) 0 ns
Hold time, CS low after last I/O CLOCK↓, t
h(CS)
0 ns
Setup time, CS low before clocking in first address bit, t
su(CS)
(see Note 3) 1.425 µs
Clock frequency at I/O CLOCK (see Note 4)
TLV1543C/TLV1543I 0 1.1
MHz
Clock frequency at I/O CLOCK (see Note 4)
TLV1543M 0 2.1
MHz
Pulse duration, I/O CLOCK high, t
w(H_I/O)
190 ns
Pulse duration, I/O CLOCK low, t
w(L_I/O)
190 ns
Transition time, I/O CLOCK, t
t(I/O)
(see Note 5) 1 µs
Transition time, ADDRESS and CS, t
t(CS)
10 µs
TLV1543C 0 70
°C
Operating free-air temperature, T
A
TLV1543I −40 85
°
C
Operating free-air temperature, T
A
TLV1543M −55 125 °C
NOTES: 2. Analog input voltages greater than that applied to REF+ convert as all ones (1111111111), while input voltages less than that applied
to REF− convert as all zeros (0000000000).
3. To minimize errors caused by noise at CS
, the internal circuitry waits for a setup time plus two falling edges of the internal system
clock after CS
↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum CS
setup time has elapsed.
4. For 11- to 16-bit transfers, after the tenth I/O CLOCK falling edge (≤ 2 V), at least one I/O clock rising edge (≥ 2 V) must occur within
9.5 µs.
5. This is the time required for the clock input signal to fall from V
IH
min to V
IL
max or to rise from V
IL
max to V
IH
min. In the vicinity of
normal room temperature, the devices function with input clock transition time as slow as 1 µs for remote data-acquisition
applications where the sensor and the A/D converter are placed several feet away from the controlling microprocessor.