Datasheet

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SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
6
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Table 2. Analog-Channel-Select Address
ANALOG INPUT
SELECTED
VALUE SHIFTED INTO
ADDRESS INPUT
SELECTED
BINARY HEX
A0 0000 0
A1 0001 1
A2 0010 2
A3 0011 3
A4 0100 4
A5 0101 5
A6 0110 6
A7 0111 7
A8 1000 8
A9 1001 9
A10 1010 A
Table 3. Test-Mode-Select Address
INTERNAL SELF-TEST
VOLTAGE SELECTED
†
VALUE SHIFTED INTO
ADDRESS INPUT
OUTPUT RESULT (HEX)
‡
VOLTAGE SELECTED
†
BINARY HEX
OUTPUT RESULT (HEX)
‡
V
ref)
–V
ref–
1011
B
200
V
ref
)
–V
ref–
2
1011 B 200
V
ref−
1100 C 000
V
ref+
1101 D 3FF
†
V
ref+
is the voltage applied to the REF+ input, and V
ref−
is the voltage applied to the REF−
input.
‡
The output results shown are the ideal values and vary with the reference stability and with
internal offsets.
converter and analog input
The CMOS threshold detector in the successive-approximation conversion system determines each bit by
examining the charge on a series of binary-weighted capacitors (see Figure 1). In the first phase of the
conversion process, the analog input is sampled by closing the S
C
switch and all S
T
switches simultaneously.
This action charges all the capacitors to the input voltage.
In the next phase of the conversion process, all S
T
and S
C
switches are opened and the threshold detector
begins identifying bits by identifying the charge (voltage) on each capacitor relative to the reference (REF−)
voltage. In the switching sequence, ten capacitors are examined separately until all ten bits are identified and
the charge-convert sequence is repeated. In the first step of the conversion phase, the threshold detector looks
at the first capacitor (weight = 512). Node 512 of this capacitor is switched to the REF+ voltage, and the
equivalent nodes of all the other capacitors on the ladder are switched to REF−. If the voltage at the summing
node is greater than the trip point of the threshold detector (approximately one-half the V
CC
voltage), a bit 0 is
placed in the output register and the 512-weight capacitor is switched to REF−. If the voltage at the summing
node is less than the trip point of the threshold detector, a bit 1 is placed in the register and the 512-weight
capacitor remains connected to REF+ through the remainder of the successive-approximation process. The
process is repeated for the 256-weight capacitor, the 128-weight capacitor, and so forth down the line until all
bits are counted.
With each step of the successive-approximation process, the initial charge is redistributed among the
capacitors. The conversion process relies on charge redistribution to count and weigh the bits from MSB to LSB.