Datasheet

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   
      
SLAS072E − DECEMBER 1992 − REVISED JANUARY 2004
14
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NOTES: A. To minimize errors caused by noise at CS, the internal circuitry waits for a set up time plus two falling edges of the internal syste
m
clock after CS↓ before responding to control input signals. No attempt should be made to clock in an address until the minimum C
S
setup time has elapsed.
B. A low-to-high transition of CS
disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges
of
the internal system clock.
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
12345678910 1
I/O
CLOCK
DATA
OUT
ADDRESS
CS
EOC
Initialize
Low
Level
Hi-Z
See Note B
11 16
(see Note A)(see Note A)
Figure 11. Timing for 11- to 16-Clock Transfer Using CS (Serial Transfer Interval Shorter Than Conversion
)
Access Cycle B
Shift in New Multiplexer Address,
Simultaneously Shift Out Previous
Conversion Value
Sample Cycle B
A/D Conversion
Interval
Initialize
MSB LSB
Previous Conversion Data
MSB LSB
B3 B2 B1 B0 C3
B9A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
Low Level
1234 56 78910 1
I/O
CLOCK
DATA
OUT
A
DDRESS
CS
EOC
Initialize
Must be High on Power Up
14 15 16
See Note B
(see Note A)
NOTES: A. The first I/O CLOCK must occur after the rising edge of EOC.
B. A low-to-high transition of CS
disables ADDRESS and the I/O CLOCK within a maximum of a setup time plus two falling edges o
f
the internal system clock.
Figure 12. Timing for 16-Clock Transfer Not Using CS (Serial Transfer Interval Shorter Than Conversion)