Datasheet

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      
    
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003
5
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
detailed description (continued)
Charge
Redistribution
DAC
Control
Logic
_
+
REFM
Ain
ADC Code
Figure 1. Simplified Model of the Successive-Approximation System
serial interface
INPUT DATA FORMAT
MSB LSB
D15−D12 D11−D0
Command ID[15:12] Configuration data field ID[11:0]
Input data is binary. All trailing blanks can be filled with zeros.
OUTPUT DATA FORMAT READ CFR
MSB LSB
D15−D12 D11−D0
Don’t care Register content OD[11:0]
OUTPUT DATA FORMAT FIFO READ
MSB LSB
D15−D12 D11−D2 D1, D0
Don’t care FIFO content OD[9:0] Don’t care
OUTPUT DATA FORMAT CONVERSION
MSB LSB
D15−D6 D5−D0
Conversion result OD[9:0] Don’t care
The output data format is binary (unipolar straight binary).
binary
Zero scale code = 000h, Vcode = VREFM
Full scale code = 3FFh, Vcode = VREFP − 1 LSB