Datasheet

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      
    
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003
34
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
PRINCIPLES OF OPERATION
GND
CS
XF
TMS320 DSP
TLV1504/
TLV1508
SDI
SDO
SCLK
INT
TXD
RXD
CLKR
BIO
10 kΩ
v
cc
A
IN
V
DD
FSR
FS
CLKX
FSX
Figure 38. Typical Interface to a TMS320 DSP
DATE CODE INFORMATION
Parts with a date code earlier than 31xxxxx have the following discrepancies:
1. Earlier devices react to FS input irrespective of the state of the CS
signal.
2. The earlier silicon was designed with SDO prereleased half clock ahead. This means in the microcontroller
mode (FS=1) the SDO is changed on the rising edge of SCLK with a delay; and for DSP serial port (when
FS is active) the SDO is changed on the falling edge of SCLK with a delay. This helps the setup time for
processor input data, but may reduce the hold time for processor input data. It is recommended that a
100 pF capacitance be added to the SDO line of the ADC when interfacing with a slower processor that
requires longer input data hold time.
3. For earlier silicon, the delay time is specified as:
DESCRIPTION TEST CONDITIONS MIN TYP MAX UNIT
Delay time, delay from SCLK falling edge (FS is ac-
V
CC
= 4.5 V
SDO = 0 pF 16
Delay time, delay from SCLK falling edge (FS is ac-
tive) or SCLK rising edge (FS=1) to next SDO valid,
V
CC
= 4.5 V
SDO = 100 pF 20
ns
tive) or SCLK rising edge (FS=1) to next SDO valid,
t
d(SCLK-DOV)
.
V
CC
= 2.7 V
SDO = 0 pF 24
ns
t
d(SCLK-DOV)
.
V
CC
= 2.7 V
SDO = 100 pF 30
This is because the SDO is changed at the rising edge in the up mode with a delay. This is the hold time
required by the external digital host processor, therefore, a minimum value is specified. The newer silicon
has been revised with SDO changed at the falling edge in the up mode with a delay. Since at least 0.5 SCLK
exist as the hold time for the external host processor, the specified maximum value helps with the
calculation of the setup time requirement of the external digital host processor.
For an explanation of the DSP mode, reverse the rising/falling edges in item (2) above.