Datasheet
SLAS251A − DECEMBER 1999 − REVISED JANUARY 2003
19
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
reference block equivalent circuit
INT REF
Close = Int Ref Used
Open = Ext Ref Used
REFM (See Note A)
Sample Convert
~50 pF
CDAC
External to the Device
10 µF
Internal
Reference
Compensation
Cap
0.1 µF
Decoupling
Cap
REFP
NOTES: A. If internal reference is used, tie REFM to analog ground and install a 10-µF (or 4.7-µF) internal reference compensation capacitor
between REFP and REFM to store the charge as shown in the figure above.
B. If external reference is used, the 10-µF (internal reference compensation) capacitor is optional. REFM can be connected to external
REFM or AGND.
C. Internal reference voltage drift, due to temperature variations, is approximately ±10 mV about the nominal 2 V (typically) from −10°C
to 100°C . The nominal value also varies approximately ±50 mV across devices.
D. Internal reference leakage during low ON time: Leakage resistance is on the order of 100 MΩ or more. This means the time constant
is about 1000 s with 10-µF compensation capacitance. Since the REF voltage does not vary much, the reference comes up quickly
after resuming from autopower-down. At power up and power down the internal reference sees a glitch of about 500 µV when 2-V
internal reference is used (1 mV when 4-V internal reference is used). This glitch settles out after about 50 µs.
power down
The device has three power-down modes.
autopower-down mode
The device enters the autopower-down state at the end of a conversion.
In autopower-down, the power consumption reduces to about 1 mA when an internal reference is selected. The
built-in reference is still on to allow the device to resume quickly. The resumption is fast enough (within 0.5
SCLK) for use between cycles. An active CS
, FS, or CSTART resumes the device from power-down state. The
power current is 1 µA when an external reference is programmed and SCLK stops.
hardware/software power-down mode
Writing 8000h to the device puts the device into a software power down state, and the entire chip (including the
built-in reference) is powered down. For a hardware power-down, the dedicated PWDN
pin provides another
way to power down the device asynchronously. These two power-down modes power down the entire device
including the built-in reference to save power. The power down current is reduced to about 1 µA is the SCLK
is stopped.
An active CS
, FS, or CSTART restores the device. There is no time delay when an external reference is selected.
However, if an internal reference is used, it takes about 20 ms to warm up. Deselect PWDN
pin to remove the
device from the hardware power-down state. This requires about 20 ms to warm up if an internal reference is
also selected.
The configuration register is not affected by any of the power down modes but the sweep operation sequence
has to be started over again. All FIFO contents are cleared by the power-down modes.