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Thermal Guidelines and Layout Recommendations

5 Thermal Guidelines and Layout Recommendations

Thermal management is a key component in the design of any power converter and is especially

important when the power dissipation in the LDO is high. Use the following formula to approximate the

maximum power dissipation for the particular ambient temperature:

= T

+ P

× θ

where T

is the junction temperature, T

is the ambient temperature, P

is the power dissipation in the

device (Watts), and θ

is the thermal resistance from junction to ambient. All temperatures are in degrees

Celsius. The maximum silicon junction temperature, T

, must not be allowed to exceed 150°C. The layout

design must be copper trace and plane areas smartly, as thermal sinks, preventing T

from exceeding the

absolute maximum rating under all temperature conditions and voltage conditions across the part.

The layout should carefully consider the thermal design of the PCB for optimal performance over

temperature. Figure 5 shows the PCB top GND plane has twenty-two 6-mil thermal via connections to the

bottom side copper GND plane to dissipate heat, for this EVM. The PCB is a two-layer board with 2 oz.

copper on the top and bottom layers. The DCY package drawing can be found at the Texas Instruments

website in the product folder for the TLV117125 LDO.

Table 1 repeats information from the Dissipation Ratings Table of the TLV117125-series datasheet. The

High-K value is determined using a standard JEDEC High-K (2s2p) board having dimensions of 3-inch x

3-inch with 1-oz internal power and ground planes and 2-oz copper traces on the top and bottom of the

board.

Table 1. Thermal Resistance, θ

, and Maximum Power Dissipation

Max Dissipation Without Derating Max Dissipation Without Derating

Board Package θ

= 25°C) (T

= 70°C)

High-K DCY 62.9°C/W 1.59 W 874 mW

6 Board layout

Figure 4. Assembly Layer

SLVU684–February 2012 TLV117125EVM-097 Evaluation Module

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