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Where T
J
is the junction temperature, T
A
is the ambient temperature, P
D
is the power dissipation in the
device (Watts), and θ
JA
is the thermal resistance from junction to ambient. All temperatures are in degrees
Celsius. The maximum silicon junction temperature, T
J
, must not be allowed to exceed 150°C. The layout
design must use copper trace and plane areas smartly, as thermal sinks, in order not to allow T
J
to exceed
the absolute maximum rating under all temperature conditions and voltage conditions across the part.
The layout should consider carefully the thermal design of the PCB for optimal performance over
temperature. For this EVM, Figure 4 shows the PCB top V
OUT
plane has twenty-four 6-mil thermal via
connections to the bottom side copper V
OUT
plane to dissipate heat. The PCB is a two layer board with
2oz. copper on top and bottom layers. The DCY package drawing can be found at the Texas Instruments
web site in the product folder for the TLV1117LVxx LDO.
Table 1 repeats information from the Dissipation Ratings Table of the TLV1117LV series data sheet for
comparison with the thermal resistance, θ
JA
, calculated for this EVM layout to show the wide variation in
thermal resistances for given copper areas. The High-K value is determined using a standard JEDEC
High-K (2s2p) board having dimensions of 3-inch x 3-inch with 1-oz internal power and ground planes and
2-oz copper traces on top and bottom of the board.
Table 1. Thermal Resistance, θ
JA
, and Maximum Power Dissipation
Max Dissipation Without Max Dissipation Without
Board Package θ
JA
Derating Derating
(T
A
= 25°C) (T
A
= 70°C)
High-K DCY 62.9°C/W 1.59 W 874 mW
TLV1117LVxxEVM-714 DCY 47.8°C/W 2.615 W 1.674 W
6 Board Layout
Figure 3. Assembly Layer
4
TLV1117LVxxEVM-714 Evaluation Module SLVU449B–March 2011–Revised May 2011
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