Datasheet

 
 
      
SLAS148 − SEPTEMBER 1996
2
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
POST OFFICE BOX 1443
• HOUSTON, TEXAS 77251−1443
functional block diagram
R
Start
Flip-Flop
S
CLK
CLK
Time
Delay
S
R
CS
DO
CS
CS
D
CLK
R
EOC
9-Bit
Shift
Register
CS
R
CLK
First
LSB
Bit 1
Bits 0−7
First
One
Shot
SAR
Logic
and
Latch
R
EN
CS
Bits 0−7
REF
Ladder
and
Decoder
EN
Comparator
EN
Analog
MUX
CH1/IN−
CH0/IN+
SGL/DIF
ODD/EVEN
Start
CLK
D
Shift Register
To Internal
Circuits
(TLV0832
only)
DI
CS
CLK
MSB
(TLV0831
only)