Datasheet

TLK3101
2.5 Gbps to 3.125 Gbps TRANSCEIVER
SCAS649B − AUGUST 2000 − REVISED JANUARY 2008
12
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
Terminal Functions
signal
TERMINAL
TYPE
DESCRIPTION
NAME NO.
TYPE
DESCRIPTION
DOUTTXP
DOUTTXN
60
59
Output
†
Serial transmit outputs. DOUTTXP and DOUTTXN are differential serial outputs that interface to copper or
an optical I/F module. These terminals transmit NRZ data at a rate of 20 times the GTX_CLK value.
DOUTTXP and DOUTTXN are put in a high-impedance state when LOOPEN is high and are active when
LOOPEN is low . During power-on-reset these pins are high-impedance.
DINRXP
DINRXN
54
53
Input Serial receive inputs. DINRXP and DINRXN together are the differential serial input interface from a copper
or an optical I/F module.
GTX_CLK 8 Input Reference clock. GTX_CLK is a continuous external input clock that synchronizes the transmitter interface
signals TX_EN, TX_ER and TXD. The frequency range of GTX_CLK is 125 MHz to 156.25 MHz. The
transmitter uses the rising edge of this clock to register the 16-bit input data (TXD) for serialization.
LCKREFN 25 Input
‡
Lock to reference. When LCKREFN is low, the receiver clock is frequency locked to GTX_CLK. This places
the device in a transmit only mode, since the receiver is not tracking the data. When LCKREFN is asserted
low, the receive data bus pins, RXD[0:15], RX_CLK and RX_ER, RX_DV/LOS are in a high-impedance
state.
When LCKREFN is deasserted high, the receiver is locked to the received data stream and must receive
valid codes from the synchronization state machine before the transmitter is enabled.
TXD0
TXD1
TXD2
TXD3
TXD4
TXD5
TXD6
TXD7
TXD8
TXD9
TXD10
TXD11
TXD12
TXD13
TXD14
TXD15
62
63
64
2
3
4
6
7
10
11
12
14
15
16
17
19
Input Transmit data bus. These inputs carry the 16-bit parallel data output from a protocol device to the transceiver
for encoding, serialization, and transmission. This 16-bit parallel data is clocked into the transceiver on the
rising edge of GTX_CLK as shown in Figure 10.
RXD0
RXD1
RXD2
RXD3
RXD4
RXD5
RXD6
RXD7
RXD8
RXD9
RXD10
RXD11
RXD12
RXD13
RXD14
RXD15
51
50
49
47
46
45
44
42
40
39
37
36
35
34
32
31
Output
†
Receive data bus. These outputs carry 16-bit parallel data output from the transceiver to the protocol device,
synchronized to RX_CLK. The data is valid on the rising edge of RX_CLK as shown in Figure 12. These pins
are in high-impedance state during power-on reset.
RX_CLK 41 Output
§
Recovered clock. Output clock that is synchronized to RXD, RX_ER, RX_DV/LOS. RX_CLK is the
recovered serial data rate clock divided by 20. RX_CLK is held low during power-on reset.
†
Hi-Z on power up
‡
Internal pullup
§
Low on power up