Datasheet

TLK3101
2.5 Gbps to 3.125 Gbps TRANSCEIVER
SCAS649B − AUGUST 2000 − REVISED JANUARY 2008
10
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
synchronization and initialization (continued)
The state of the transmit data bus, control pins, and serial outputs during the link acquisition process is illustrated
in Figure 7.
ACQ
D0−D15
DOUTTXP,
DOUTTXN
TXD(0−15)
TX_ER
Ca. Ext.
Error
IDLE
SYNC
TX_EN
D0−D15
xx xx xx xxxxxxxx
xx xx xx xx xx xx xx
xx xxxxxxxx xx xx xx
Figure 7. Transmit Side Timing Diagram
The state of the receive data bus, status pins, and serial inputs during the link acquisition process is illustrated
in Figure 8 and Figure 9.
ACQ
RX_DV,
RX_ER
RXD(0−15)
SYNC
DINRXP,
D0−D15
IDLE or Carrier
Extend
IDLE or Carrier
Extend
IDLE or Carrier
Extend
DINRXN
D0−D15
IDLE or Carrier
Extend
IDLE or Carrier
Extend
XXXXXXXXXXXXXXXXXXX
RESET
(Internal Signal)
Figure 8. Receive Side Timing Diagram (IDLE or Carrier Extend)
ACQ
RX_DV,
RX_ER
RXD(0−15)
SYNC
DINRXP,
D0−D15
DINRXN
D0−D15
Valid Data or
Error Prop
XXXXXXXXXXXXXXXXXXX
RESET
(Internal Signal)
IDLE D0−D15
D0−D15
Valid Data or
Error Prop
Figure 9. Receive Side Timing Diagram (Valid Data or Error Propagation)