Datasheet

TLK2711A
www.ti.com SLLS908B –JULY 2008–REVISED OCTOBER 2012
High-Speed Data Output
The high-speed data output driver consists of a voltage mode logic (VML) differential pair optimized for a 50-Ω
impedance environment. The magnitude of the differential pair signal swing is compatible with pseudo emitter
coupled logic (PECL) levels when ac-coupled. The line can be directly-coupled or ac-coupled. Refer to Figure 11
and Figure 12 for termination details. The outputs also provide preemphasis to compensate for ac loss when
driving a cable or PCB backplane trace over a long distance (see Figure 4). The level of pre-emphasis is
controlled by PRE as shown in Table 2.
Table 2. Programmable Pre-emphasis
PRE PRE-EMPHASIS LEVEL(%)
V
OD(P)
, V
OD(D)
(1)
0 5%
1 20%
(1) V
OD(p)
: Voltage swing when there is a transition in the data
stream.
Figure 4. Output Voltage Under Pre-emphasis
V
OD(d)
: Voltage swing when there is no transition in the data
(|VTXP–VTXN|) stream.
Receive Interface
The receiver portion of the TLK2711A accepts 8-bit/10-bit encoded differential serial data. The interpolator and
clock recovery circuit locks to the data stream and extract the bit rate clock. This recovered clock is used to
retime the input data stream. The serial data is then aligned to two separate 10-bit word boundaries, 8-bit/10-bit
decoded and output on a 16-bit wide parallel bus synchronized to the extracted receive clock. The data is
received LSB (RXD0) first.
Receive Data Bus
The receive bus interface drives 16-bit wide single-ended TTL parallel data at the RXD[0:15] terminals. Data is
valid on the rising edge of the RXCLK. The RXCLK is used as the recovered word clock. The data, RKLSB,
RKMSB, and clock signals are aligned as shown in Figure 5. Detailed timing information can be found in the
switching characteristics table.
Figure 5. Receive Timing Waveform
Data Reception Latency
The serial-to-parallel data receive latency is the time from when the first bit arrives at the receiver until it is output
in the aligned parallel word. The receive latency is fixed once the link is established. However, due to silicon
process variations and implementation variables such as supply voltage and temperature, the exact delay varies
slightly. The minimum receive latency t
d(Rx latency)
is 76 bit times; the maximum is 107 bit times. Figure 6 illustrates
the timing relationship between the serial receive terminals, the recovered word clock (RXCLK), and the receive
data bus.
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