Datasheet

TLK2711A
SLLS908B –JULY 2008–REVISED OCTOBER 2012 www.ti.com
TRANSMITTER/RECEIVER CHARACTERISTICS
PARAMETER TEST CONDITIONS MIN NOM MAX UNIT
R
t
= 50Ω, PREM = high, dc-coupled, See 655 800 1100
Figure 9
Preemphasis V
OD
, direct,
V
OD(p)
mV
V
OD(p)
= |VTXP – VTXN|
Rt = 50Ω, PREM = low, dc-coupled, See 590 740 1050
Figure 9
R
t
= 50Ω, PREM = high, dc-coupled, See 1310 1600 2200
Figure 9
Differential peak-to-peak output voltage
V
OD( pp_p)
mV
PP
with preemphasis
Rt = 50Ω, PREM = low, dc-coupled, See 1180 1480 2100
Figure 9
V
OD(d)
Deemphais output voltage, R
t
= 50 Ω, DC-coupled, See Figure 9 540 650 950 mV
|VTXP–VTXN|
V
OD(pp_d)
Differential, peak-to-peak output R
t
= 50Ω, dc-coupled, See Figure 9 1080 1300 1900 mV
PP
voltage with deemphasis
V
(cmt)
Transmit common mode voltage range, R
t
= 50Ω, See Figure 9 1000 1250 1400 mV
(VTXP + VTXN)/2
V
ID
Receiver input voltage differential, 200 1600 mV
|VRXP – VRXN|
Receiver common mode voltage range, 1000 1250 2250
V
(cmr)
mV
(VRXP + VRXN)/2
I
lkg
Receiver input leakage current –10 10 μA
Ci Receiver input capacitance 2 pF
Differential output jitter at 2.7 Gbps, Random 0.20
+ deterministic, PRBS pattern
Serial data total jitter (peak-to-peak) UI
(1)
Differential output jitter at 1.5 Gbps, Random 0.16
+ deterministic, PRBS pattern
t
t
, t
f
Differential output signal rise, fall time R
L
= 50Ω, C
L
= 5 pF, See Figure 9 150 ps
(20% to 80%)
Jitter tolerance Differential input jitter, random + 0.60 UI
deterministic, PRBS pattern at zero crossing
t
d(Tx latency)
Tx latency See Figure 3 34 38 bits
t
d(Rx latency)
Rx latency See Figure 6 76 107 bits
(1) UI is the time interval of one serialized bit.
Figure 9. Differential and Common-Mode Output Voltage Definitions
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