Datasheet

TLK2711A
www.ti.com SLLS908B –JULY 2008–REVISED OCTOBER 2012
Table 3. Receive Status Signals
RKLSB RKMSB DECODED 20 BIT OUTPUT
0 0 Valid data on RXD(0–7), Valid data RXD(8–15)
0 1 Valid data on RXD(0–7), K code on RXD(8–15))
1 0 K code on RXD(0–7), Valid data on RXD(8–15)
1 1 K code on RXD(0–7), K code on RXD(8–15)
Table 4. Valid K Characters
K CHARACTER RECEIVE DATA BUS
(RXD[7–0]) OR (RXD[15–8])
K28.0 000 11100
K28.1
(1)
001 11100
K28.2 010 11100
K28.3 011 11100
K28.4 100 11100
K28.5
(1)
101 11100
K28.6 110 11100
K28.7
(1)
111 11100
K23.7 111 10111
K27.7 111 11011
K29.7 111 11101
K30.7 111 11110
(1) Should only be present on RXD[7-0] when in running disparity < 0.
Power Down Mode
When the ENABLE pin is pulled low, the TLK2711A goes into power-down mode. In the power-down mode, the
serial transmit pins (TXN), the receive data bus pins (RXD[0:15]), and RKLSB goes into a high-impedance state.
In the power-down condition, the signal detection circuit draws less than 15 mW. When the TLK2711A is in the
power-down mode, the clock signal on the TXCLK terminal must be provided.
Loss of Signal Detection
The TLK2711A has a loss of signal detection circuit for conditions where the incoming signal no longer has a
sufficient voltage level to keep the clock recovery circuit in lock. The signal detection circuit is intended to be an
indication of gross signal error conditions, such as a detached cable or no signal being transmitted, and not an
indication of signal coding health. The TLK2711A reports this condition by asserting RKLSB, RKMSB and
RXD[0:15] terminals to a high state. As long as the differential signal is above 200 mV in differential magnitude,
the LOS circuit does not signal an error condition.
PRBS Verification
The TLK2711A also has a built-in BERT function in the receiver side that is enabled by the PRBSEN. It can
check for errors and report the errors by forcing the RKLSB terminal low.
Reference Clock Input
The reference clock (TXCLK) is an external input clock that synchronizes the transmitter interface. The reference
clock is then multiplied in frequency 10 times to produce the internal serialization bit clock. The internal
serialization bit clock is frequency-locked to the reference clock and used to clock out the serial transmit data on
both its rising and falling edges, providing a serial data rate that is 20 times the reference clock.
Operating Frequency Range
The TLK2711A can operate at a serial data rate from 1.6 Gbps to 2.7 Gbps. To achieve these serial rates,
TXCLK must be within 80 MHz to 135 MHz. The TXCLK must be within ±100 PPM of the desired parallel data
rate clock.
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