Datasheet

TLK2711A

SLLS908B –JULY 2008–REVISED OCTOBER 2012

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Figure 6. Receiver Latency

Serial-to-Parallel

Serial data is received on the RXP and RXN terminals. The interpolator and clock recovery circuit locks to the

data stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock. The

recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel

shift registers. The 10-bit wide parallel data is then multiplexed and fed into two separate 8-bit/10-bit decoders

where the data is then synchronized to the incoming data stream word boundary by detection of the comma 8-

bit/10-bit synchronization pattern.

Common Detect and 8-Bit/10-Bit Decoding

The TLK2711A has two parallel 8-bit/10-bit decode circuits. Each 8-bit/10-bit decoder converts 10 bit encoded

data (half of the 20-bit received word) back into 8 bits. The comma detect circuit is designed to provide for byte

synchronization to an 8-bit/10-bit transmission code. When parallel data is clocked into a parallel to serial

converter, the byte boundary that was associated with the parallel data is now lost in the serialization of the data.

When the serial data is received and converted to parallel format again, a method is needed to recognize the

byte boundary. Generally this is accomplished through the use of a synchronization pattern. This is generally a

unique pattern of 1's and 0's that either cannot occur as part of valid data or is a pattern that repeats at defined

intervals. The 8-bit/10-bit encoding contains a character called the comma (b0011111 or b1100000), which is

used by the comma detect circuit on the TLK2711A to align the received serial data back to its original byte

boundary. The decoder detects the comma, generating a synchronization signal aligning the data to their 10-bit

boundaries for decoding; the comma is mapped into the LSB. The decoder then converts the data back into 8-bit

data. The output from the two decoders is latched into the 16-bit register synchronized to the recovered parallel

data clock (RXCLK) and output valid on the rising edge of the RXCLK.

NOTE

The TLK2711A only achieves byte alignment on the 0011111 comma.

Decoding provides two additional status signals, RKLSB and RKMSB. When RKLSB is asserted , an 8-bit/10-bit

K code was received and the specific K code is presented on the data bits RXD0–RXD7; otherwise, an 8-bit/10-

bit D code was received. When RKMSB is asserted, an 8-bit/10-bit K code was received and the specific K-code

is presented on data bits RXD8–RXD15; otherwise, an 8-bit/10-bit D code was received (see Table 3). The valid

K codes the TLK2711A decodes are provided in Table 4. An error detected on either byte, including K codes not

in Table 4, causes that byte only to indicate a K0.0 code on the RK×SB and associated data pins, where K0.0 is

known to be an invalid 8-bit/10-bit code. A loss of input signal causes a K31.7 code to be presented on both

bytes, where K31.7 is also known to be an invalid 8-bit/10-bit code.

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