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TLK2711A

www.ti.com

SLLS908B –JULY 2008–REVISED OCTOBER 2012

1.6 TO 2.7 GBPS TRANSCEIVER

Check for Samples: TLK2711A

FEATURES

• On-Chip PLL Provides Clock Synthesis From

Low-Speed Reference

• 1.6 to 2.7 Gigabits Per Second (Gbps)

• Receiver Differential Input Thresholds 200 mV

Serializer/Deserializer

Minimum

• Hot-Plug Protection

• Low Power: < 500 mW

• High-Performance 80-Pin BGA Microstar

• 3 V Tolerance on Parallel Data Input Signals

Junior™ Package (GQE)

• 16-Bit Parallel TTL Compatible Data Interface

• 2.5-V Power Supply for Low Power Operation

• Ideal for High-Speed Backplane Interconnect

• Programmable Preemphasis Levels on Serial

and Point-to-Point Data Link

Output

• Industrial Temperature Range (–40°C to 85°C

• Interfaces to Backplane, Copper Cables, or

RCP Package Only)

Optical Converters

• Loss of Signal (LOS) Detection

• On-Chip 8-bit/10-bit Encoding/Decoding,

Comma Detect

• Integrated 50-Ω Termination Resistors on RX

DESCRIPTION

The TLK2711A is a member of the WizardLink transceiver family of multigigabit transceivers, intended for use in

ultrahigh-speed bidirectional point-to-point data transmission systems. The TLK2711A supports an effective serial

interface speed of 1.6 Gbps to 2.7 Gbps, providing up to 2.16 Gbps of data bandwidth.

The primary application of this chip is to provide very high-speed I/O data channels for point-to-point baseband

data transmission over controlled impedance media of approximately 50Ω. The transmission media can be

printed-circuit board, copper cables, or fiber-optic cable. The maximum rate and distance of data transfer is

dependent upon the attenuation characteristics of the media and the noise coupling to the environment.

This device can also be used to replace parallel data transmission architectures by providing a reduction in the

number of traces, connector terminals, and transmit/receive terminals. Parallel data loaded into the transmitter is

delivered to the receiver over a serial channel, which can be a coaxial copper cable, a controlled impedance

backplane, or an optical link. It is then reconstructed into its original parallel format. It offers significant power and

cost savings over parallel solutions, as well as scalability for higher data rates in the future.

The TLK2711A performs data conversion parallel-to-serial and serial-to-parallel. The clock extraction functions as

a physical layer interface device. The serial transceiver interface operates at a maximum speed of 2.7 Gbps. The

transmitter latches 16-bit parallel data at a rate based on the supplied reference clock (TXCLK). The 16-bit

parallel data is internally encoded into 20 bits using an 8-bit/10-bit (8b/10b) encoding format. The resulting 20-bit

word is then transmitted differentially at 20 times the reference clock (TXCLK) rate. The receiver section

performs the serial-to-parallel conversion on the input data, synchronizing the resulting 20-bit wide parallel data

to the recovered clock (RXCLK). It then decodes the 20-bit wide data using the 8-bit/10-bit decoding format

resulting in 16 bits of parallel data at the receive data terminals (RXD0-15). The outcome is an effective data

payload of 2 Gbps to 2.5 Gbps (16 bits data x the frequency).

The TLK2711A is provided in two packages options: a 80-pin ball grid array MicroStar Junior package and a 64-

pin VQFP (RCP) package.

The TLK2711A provides an internal loopback capability for self-test purposes. Serial data from the serializer is

passed directly to the deserializer, providing the protocol device with a functional self-check of the physical

interface.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2Microstar Junior, PowerPAD are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (28 pages)

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TLK2711A www.ti.com SLLS908B – JULY 2008 – REVISED OCTOBER 2012 1.6 TO 2.7 GBPS TRANSCEIVER Check for Samples: TLK2711A FEATURES 1 • 2 • • • • • • 1.6 to 2.7 Gigabits Per Second (Gbps) Serializer/Deserializer Hot-Plug Protection High-Performance 80-Pin BGA Microstar Junior™ Package (GQE) 2.
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TLK2711A SLLS908B – JULY 2008 – REVISED OCTOBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. DESCRIPTION (CONTINUED) The TLK2711A has a loss of signal (LOS) detection circuit for conditions where the incoming signal no longer has a sufficient voltage amplitude to keep the clock recovery circuit in lock.
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TLK2711A www.ti.
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TLK2711A SLLS908B – JULY 2008 – REVISED OCTOBER 2012 www.ti.com BLOCK DIAGRAM Figure 1.
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TLK2711A www.ti.com SLLS908B – JULY 2008 – REVISED OCTOBER 2012 TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION I (1) Device enable. When this terminal is held low, the device is placed in power-down mode. Only the signal detect circuit on the serial receive pair is active. When asserted high while the device is in power-down mode, the transceiver goes into power-on reset before beginning normal operation.
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TLK2711A SLLS908B – JULY 2008 – REVISED OCTOBER 2012 www.ti.com TERMINAL FUNCTIONS (Continued) TERMINAL NAME NO. I/O GQE RCP RXD0 RXD1 RXD2 RXD3 RXD4 RXD5 RXD6 RXD7 RXD8 RXD9 RXD10 RXD11 RXD12 RXD13 RXD14 RXD15 H3 J2 H2 H1 G2 G1 F2 F1 E1 D1 C1 D2 C2 B1 B2 A2 51 50 49 47 46 45 44 42 40 39 37 36 35 34 32 31 RXN RXP J3 J4 DINRXN DINRXP TESTEN O I 53 54 B4 (2) K-code generator (LSB). When TKLSB is high, an 8-bit/10-bit K code is transmitted as controlled by data bits TXD0–TXD7.
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TLK2711A www.ti.com SLLS908B – JULY 2008 – REVISED OCTOBER 2012 TERMINAL FUNCTIONS (Continued) TERMINAL NAME VDD VDDA NO. I/O GQE RCP C5, D5, E5, F5, G5, C6, D6, E6, F6, G6, C7, D7, E7, F7, G7, E8 1, 9, 23, 38, 48 H5 55, 57 DESCRIPTION Digital logic power. Provides power for all digital circuitry and digital I/O buffers. Analog power. VDDA provides a supply reference for the high-speed analog circuits, receiver and transmitter.
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TLK2711A SLLS908B – JULY 2008 – REVISED OCTOBER 2012 www.ti.com Figure 3. Transmission Latency 8-Bit/10-Bit Encoder All true serial interfaces require a method of encoding to insure minimum transition density so that the receiving PLL has a minimal number of transitions to stay locked on. The encoding scheme maintains the signal dc balance by keeping the number of ones and zeros the same. This provides good transition density for clock recovery and improves error checking.
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TLK2711A www.ti.com SLLS908B – JULY 2008 – REVISED OCTOBER 2012 High-Speed Data Output The high-speed data output driver consists of a voltage mode logic (VML) differential pair optimized for a 50-Ω impedance environment. The magnitude of the differential pair signal swing is compatible with pseudo emitter coupled logic (PECL) levels when ac-coupled. The line can be directly-coupled or ac-coupled. Refer to Figure 11 and Figure 12 for termination details.
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TLK2711A SLLS908B – JULY 2008 – REVISED OCTOBER 2012 www.ti.com Figure 6. Receiver Latency Serial-to-Parallel Serial data is received on the RXP and RXN terminals. The interpolator and clock recovery circuit locks to the data stream if the clock to be recovered is within 200 PPM of the internally generated bit rate clock. The recovered clock is used to retime the input data stream. The serial data is then clocked into the serial-to-parallel shift registers.
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TLK2711A www.ti.com SLLS908B – JULY 2008 – REVISED OCTOBER 2012 Table 3. Receive Status Signals RKLSB RKMSB 0 0 Valid data on RXD(0–7), DECODED 20 BIT OUTPUT Valid data RXD(8–15) 0 1 Valid data on RXD(0–7), K code on RXD(8–15)) 1 0 K code on RXD(0–7), Valid data on RXD(8–15) 1 1 K code on RXD(0–7), K code on RXD(8–15) Table 4. Valid K Characters (1) K CHARACTER RECEIVE DATA BUS (RXD[7–0]) OR (RXD[15–8]) K28.0 000 11100 K28.1 (1) 001 11100 K28.2 010 11100 K28.3 011 11100 K28.
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TLK2711A SLLS908B – JULY 2008 – REVISED OCTOBER 2012 www.ti.com Testability The TLK2711A has a comprehensive suite of built-in self-tests. The loopback function provides for at-speed testing of the transmit/receive portions of the circuitry. The enable terminal allows for all circuitry to be disabled so that a quiescent current test can be performed. The PRBS function allows for BIST (built-in self-test).
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TLK2711A www.ti.com SLLS908B – JULY 2008 – REVISED OCTOBER 2012 DISSIPATION RATINGS (continued) (3) (4) PACKAGE TA ≤ 25°C POWER RATING DERATING FACTOR (1) ABOVE TA = 25°C TA = 70°C POWER RATING RCP64 (3) 3.17 W 23.70 mW/°C 1.74 W RCP64 (4) 2.01 W 13.19 mW/°C 1.11 W 2 oz. Trace and copper pad without solder. Standard JEDEC High-K board. For more information, refer to TI application note PowerPAD™ Thermally Enhanced package, TI literature number SLMA002.
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TLK2711A SLLS908B – JULY 2008 – REVISED OCTOBER 2012 www.ti.com Figure 7.
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TLK2711A www.ti.com SLLS908B – JULY 2008 – REVISED OCTOBER 2012 TTL OUTPUT SWITCHING CHARACTERISTICS over recommended operating conditions (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VOH High-level output voltage IOH = –1 mA, VDD = MIN 2.10 2.3 VOL Low-level output voltage IOL = 1 mA, VDD = MIN GND 0.25 tr(slew) Slew rate (rising), magnitude of RXCLK, RKLSB, RKMSB, RXD[0..15] 0.8 V to 2 V, C = 5 pF, See Figure 8 0.
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TLK2711A SLLS908B – JULY 2008 – REVISED OCTOBER 2012 www.ti.
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TLK2711A www.ti.com SLLS908B – JULY 2008 – REVISED OCTOBER 2012 THERMAL INFORMATION THERMAL CHARACTERISTICS PARAMETER RθJA RθJC Junction-to-free-air thermal resistance Junction-to-case thermal resistance TEST CONDITIONS MIN TYP Board-mounted, no air flow, high conductivity TI recommended test board, chip soldered or greased to thermal land 21.
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TLK2711A SLLS908B – JULY 2008 – REVISED OCTOBER 2012 www.ti.com Figure 11. High-Speed I/O Directly-Coupled Mode Figure 12.
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TLK2711A www.ti.com SLLS908B – JULY 2008 – REVISED OCTOBER 2012 REVISION HISTORY Changes from Original (July 2008) to Revision A • Page Changed invalid K-codes to correct typographical errors (Table 4) ................................................................................... 11 Changes from Revision A (September 2009) to Revision B • Page Changed the TYP and MAX values of VOD(p) , VOD( pp_p), VOD(d) , and VOD(pp_d) in the TRANSMITTER/RECEIVER CHARACTERISTICS table ..........................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TLK2711AIRCPR Package Package Pins Type Drawing HVQFP RCP 64 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 13.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 13.0 1.5 16.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 4-Oct-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TLK2711AIRCPR HVQFP RCP 64 1000 367.0 367.0 45.
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